2923504780
Add select for GEN_HANDLERS to use the more efficient generated interrupt handlers. Add select for HIFI3, which are the SIMD related registers. Signed-off-by: Mike J. Chen <mjchen@google.com>
88 lines
2 KiB
Text
88 lines
2 KiB
Text
# Copyright 2024 NXP
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# Copyright (c) 2023 Google LLC.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_MIMXRT595S_CM33
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select CPU_CORTEX_M33
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select CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select ARM
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select HAS_PM
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select HAS_POWEROFF
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select SOC_RESET_HOOK
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select HAS_MCUX
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select HAS_MCUX_SYSCON
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select HAS_MCUX_FLEXCOMM
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select HAS_MCUX_FLEXSPI
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select HAS_MCUX_CACHE
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select HAS_MCUX_LPC_DMA
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select HAS_MCUX_LPADC
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select HAS_MCUX_OS_TIMER
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select HAS_MCUX_LPC_RTC
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select HAS_MCUX_TRNG
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select HAS_MCUX_SCTIMER
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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select HAS_MCUX_USB_LPCIP3511
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select HAS_MCUX_CTIMER
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select SOC_EARLY_INIT_HOOK
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config SOC_MIMXRT595S_F1
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select XTENSA
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
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select XTENSA_CPU_HAS_HIFI3
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select XTENSA_GEN_HANDLERS
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select XTENSA_RESET_VECTOR
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select XTENSA_USE_CORE_CRT1
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if SOC_SERIES_IMXRT5XX
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if NXP_IMXRT_BOOT_HEADER
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config IMAGE_VECTOR_TABLE_OFFSET
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default 0x1000
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endif # NXP_IMXRT_BOOT_HEADER
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config IMXRT5XX_CODE_CACHE
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bool "Code cache"
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default y
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help
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Enable code cache for FlexSPI region at boot. If this Kconfig is
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cleared, the CACHE64 controller will be disabled during SOC init
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choice FLEXCOMM0_CLK_SRC
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prompt "Clock source for Flexcomm0"
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default FLEXCOMM0_CLK_SRC_FRG
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config FLEXCOMM0_CLK_SRC_FRG
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bool "FRG is source of Flexcomm0 clock"
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config FLEXCOMM0_CLK_SRC_FRO
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bool "FRO_DIV4 is source of Flexcomm0 clock"
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endchoice
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choice MIPI_DPHY_CLK_SRC
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prompt "Clock source for MIPI DPHY"
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default MIPI_DPHY_CLK_SRC_AUX1_PLL
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config MIPI_DPHY_CLK_SRC_AUX1_PLL
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bool "AUX1_PLL is source of MIPI_DPHY clock"
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config MIPI_DPHY_CLK_SRC_FRO
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bool "FRO 192/96M is source of MIPI_DPHY clock"
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endchoice
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config MCUX_CORE_SUFFIX
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default "_cm33" if SOC_MIMXRT595S_CM33
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default "_dsp" if SOC_MIMXRT595S_F1
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endif # SOC_SERIES_IMXRT5XX
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