279cc2e448
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the SiFive Freedom processor
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*/
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#ifndef __RISCV32_SIFIVE_FREEDOM_SOC_H_
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#define __RISCV32_SIFIVE_FREEDOM_SOC_H_
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#include <soc_common.h>
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/* PINMUX Configuration */
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#define SIFIVE_PINMUX_0_BASE_ADDR (CONFIG_SIFIVE_GPIO_0_BASE_ADDR + 0x38)
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/* PINMUX IO Hardware Functions */
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#define SIFIVE_PINMUX_IOF0 0x00
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#define SIFIVE_PINMUX_IOF1 0x01
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/* PINMUX MAX PINS */
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#define SIFIVE_PINMUX_PINS 32
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/* Platform Level Interrupt Controller Configuration */
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#define PLIC_PRIO_BASE_ADDR PLIC_BASE_ADDRESS
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#define PLIC_IRQ_EN_BASE_ADDR (PLIC_BASE_ADDRESS + 0x2000)
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#define PLIC_REG_BASE_ADDR (PLIC_BASE_ADDRESS + 0x200000)
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#define PLIC_MAX_PRIORITY PLIC_RISCV_MAX_PRIORITY
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x10008000
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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/* Always ON Domain */
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#define SIFIVE_PMUIE 0x10000140
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#define SIFIVE_PMUCAUSE 0x10000144
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#define SIFIVE_PMUSLEEP 0x10000148
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#define SIFIVE_PMUKEY 0x1000014C
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#define SIFIVE_SLEEP_KEY_VAL 0x0051F15E
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#define SIFIVE_BACKUP_REG_BASE 0x10000080
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
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#define RISCV_RAM_SIZE CONFIG_RISCV_RAM_SIZE
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#endif /* __RISCV32_SIFIVE_FREEDOM_SOC_H_ */
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