1f9beb193f
The last external reference to these was removed when the pin write/read functions were deprecated. Remove the syscall support, API function table entries, and implementation from all drivers. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
425 lines
12 KiB
C
425 lines
12 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <errno.h>
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#include <drivers/gpio.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/clock_control/arm_clock_control.h>
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#include "gpio_cmsdk_ahb.h"
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#include "gpio_utils.h"
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/**
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* @brief GPIO driver for ARM CMSDK AHB GPIO
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*/
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typedef void (*gpio_config_func_t)(struct device *port);
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struct gpio_cmsdk_ahb_cfg {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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volatile struct gpio_cmsdk_ahb *port;
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gpio_config_func_t gpio_config_func;
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/* GPIO Clock control in Active State */
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struct arm_clock_control_t gpio_cc_as;
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/* GPIO Clock control in Sleep State */
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struct arm_clock_control_t gpio_cc_ss;
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/* GPIO Clock control in Deep Sleep State */
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struct arm_clock_control_t gpio_cc_dss;
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};
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struct gpio_cmsdk_ahb_dev_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* list of callbacks */
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sys_slist_t gpio_cb;
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};
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static int gpio_cmsdk_ahb_port_get_raw(struct device *dev, u32_t *value)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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*value = cfg->port->data;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_set_masked_raw(struct device *dev, u32_t mask,
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u32_t value)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout = (cfg->port->dataout & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_cmsdk_ahb_port_set_bits_raw(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout |= mask;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_clear_bits_raw(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout &= ~mask;
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return 0;
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}
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static int gpio_cmsdk_ahb_port_toggle_bits(struct device *dev, u32_t mask)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->dataout ^= mask;
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return 0;
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}
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static int cmsdk_ahb_gpio_config(struct device *dev, u32_t mask, int flags)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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if (((flags & GPIO_INPUT) == 0) && ((flags & GPIO_OUTPUT) == 0)) {
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return -ENOTSUP;
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}
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/*
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* Setup the pin direction
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* Output Enable:
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* 0 - Input
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* 1 - Output
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*/
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if ((flags & GPIO_OUTPUT) != 0) {
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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gpio_cmsdk_ahb_port_set_bits_raw(dev, mask);
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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gpio_cmsdk_ahb_port_clear_bits_raw(dev, mask);
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}
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cfg->port->outenableset = mask;
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} else {
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cfg->port->outenableclr = mask;
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}
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cfg->port->altfuncclr = mask;
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return 0;
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}
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/**
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* @brief Configure pin or port
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*
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* @param dev Device struct
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* @param access_op Access operation (pin or port)
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_cmsdk_ahb_config(struct device *dev, int access_op,
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u32_t pin, int flags)
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{
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int ret = 0;
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switch (access_op) {
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case GPIO_ACCESS_BY_PIN:
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ret = cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
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break;
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case GPIO_ACCESS_BY_PORT:
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ret = cmsdk_ahb_gpio_config(dev, (0xFFFF), flags);
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break;
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default:
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return -ENOTSUP;
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}
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return ret;
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}
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static int gpio_cmsdk_ahb_pin_interrupt_configure(struct device *dev,
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unsigned int pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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if (trig == GPIO_INT_TRIG_BOTH) {
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return -ENOTSUP;
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}
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/* For now treat level interrupts as not supported, as we seem to only
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* get a single 'edge' still interrupt rather than continuous
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* interrupts until the cause is cleared */
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if (mode == GPIO_INT_MODE_LEVEL) {
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return -ENOTSUP;
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}
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if (mode == GPIO_INT_MODE_DISABLED) {
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cfg->port->intenclr = BIT(pin);
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} else {
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if (mode == GPIO_INT_MODE_EDGE) {
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cfg->port->inttypeset = BIT(pin);
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} else {
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/* LEVEL */
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cfg->port->inttypeclr = BIT(pin);
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}
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/* Level High or Edge Risising */
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if (trig == GPIO_INT_TRIG_HIGH) {
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cfg->port->intpolset = BIT(pin);
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} else {
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cfg->port->intpolclr = BIT(pin);
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}
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cfg->port->intclear = BIT(pin);
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cfg->port->intenset = BIT(pin);
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}
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return 0;
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}
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static void gpio_cmsdk_ahb_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
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u32_t int_stat;
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int_stat = cfg->port->intstatus;
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/* clear the port interrupts */
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cfg->port->intclear = int_stat;
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gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
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}
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static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
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return gpio_manage_callback(&data->gpio_cb, callback, set);
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}
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static int gpio_cmsdk_ahb_enable_callback(struct device *dev,
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u32_t pin)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->intenset |= BIT(pin);
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return 0;
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}
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static int gpio_cmsdk_ahb_disable_callback(struct device *dev,
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u32_t pin)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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cfg->port->intenclr |= BIT(pin);
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return 0;
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}
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static const struct gpio_driver_api gpio_cmsdk_ahb_drv_api_funcs = {
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.config = gpio_cmsdk_ahb_config,
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.port_get_raw = gpio_cmsdk_ahb_port_get_raw,
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.port_set_masked_raw = gpio_cmsdk_ahb_port_set_masked_raw,
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.port_set_bits_raw = gpio_cmsdk_ahb_port_set_bits_raw,
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.port_clear_bits_raw = gpio_cmsdk_ahb_port_clear_bits_raw,
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.port_toggle_bits = gpio_cmsdk_ahb_port_toggle_bits,
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.pin_interrupt_configure = gpio_cmsdk_ahb_pin_interrupt_configure,
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.manage_callback = gpio_cmsdk_ahb_manage_callback,
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.enable_callback = gpio_cmsdk_ahb_enable_callback,
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.disable_callback = gpio_cmsdk_ahb_disable_callback,
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};
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/**
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* @brief Initialization function of GPIO
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*
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* @param dev Device struct
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* @return 0 if successful, failed otherwise.
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*/
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static int gpio_cmsdk_ahb_init(struct device *dev)
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{
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const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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struct device *clk =
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device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->gpio_cc_as);
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clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_ss);
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clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#endif /* CONFIG_CLOCK_CONTROL */
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cfg->gpio_config_func(dev);
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return 0;
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}
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/* Port 0 */
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#ifdef CONFIG_GPIO_CMSDK_AHB_PORT0
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static void gpio_cmsdk_ahb_config_0(struct device *dev);
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static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_ARM_CMSDK_GPIO_NGPIOS),
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},
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.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0),
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.gpio_config_func = gpio_cmsdk_ahb_config_0,
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.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_AHB_GPIO0,},
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.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
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.device = DT_CMSDK_AHB_GPIO0,},
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.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_AHB_GPIO0,},
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};
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static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data;
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DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0,
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CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME,
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gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_0_data,
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&gpio_cmsdk_ahb_0_cfg, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_cmsdk_ahb_drv_api_funcs);
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static void gpio_cmsdk_ahb_config_0(struct device *dev)
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{
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IRQ_CONNECT(DT_IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI,
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gpio_cmsdk_ahb_isr,
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DEVICE_GET(gpio_cmsdk_ahb_0), 0);
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irq_enable(DT_IRQ_PORT0_ALL);
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}
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#endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */
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/* Port 1 */
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#ifdef CONFIG_GPIO_CMSDK_AHB_PORT1
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static void gpio_cmsdk_ahb_config_1(struct device *dev);
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static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_ARM_CMSDK_GPIO_NGPIOS),
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},
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.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1),
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.gpio_config_func = gpio_cmsdk_ahb_config_1,
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.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_AHB_GPIO1,},
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.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
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.device = DT_CMSDK_AHB_GPIO1,},
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.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_AHB_GPIO1,},
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};
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static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data;
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DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1,
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CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME,
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gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_1_data,
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&gpio_cmsdk_ahb_1_cfg, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_cmsdk_ahb_drv_api_funcs);
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static void gpio_cmsdk_ahb_config_1(struct device *dev)
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{
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IRQ_CONNECT(DT_IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI,
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gpio_cmsdk_ahb_isr,
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DEVICE_GET(gpio_cmsdk_ahb_1), 0);
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irq_enable(DT_IRQ_PORT1_ALL);
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}
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#endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */
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/* Port 2 */
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#ifdef CONFIG_GPIO_CMSDK_AHB_PORT2
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static void gpio_cmsdk_ahb_config_2(struct device *dev);
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static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_ARM_CMSDK_GPIO_NGPIOS),
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},
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.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2),
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.gpio_config_func = gpio_cmsdk_ahb_config_2,
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.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_AHB_GPIO2,},
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.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
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.device = DT_CMSDK_AHB_GPIO2,},
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.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_AHB_GPIO2,},
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};
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static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data;
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DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2,
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CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME,
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gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_2_data,
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&gpio_cmsdk_ahb_2_cfg, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_cmsdk_ahb_drv_api_funcs);
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static void gpio_cmsdk_ahb_config_2(struct device *dev)
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{
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IRQ_CONNECT(DT_IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI,
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gpio_cmsdk_ahb_isr,
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DEVICE_GET(gpio_cmsdk_ahb_2), 0);
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irq_enable(DT_IRQ_PORT2_ALL);
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}
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#endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */
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/* Port 3 */
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#ifdef CONFIG_GPIO_CMSDK_AHB_PORT3
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static void gpio_cmsdk_ahb_config_3(struct device *dev);
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static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_ARM_CMSDK_GPIO_NGPIOS),
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},
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.port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3),
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.gpio_config_func = gpio_cmsdk_ahb_config_3,
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.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_AHB_GPIO3,},
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.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
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.device = DT_CMSDK_AHB_GPIO3,},
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.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_AHB_GPIO3,},
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};
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static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data;
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DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3,
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CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME,
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gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_3_data,
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&gpio_cmsdk_ahb_3_cfg, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_cmsdk_ahb_drv_api_funcs);
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static void gpio_cmsdk_ahb_config_3(struct device *dev)
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{
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IRQ_CONNECT(DT_IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI,
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gpio_cmsdk_ahb_isr,
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DEVICE_GET(gpio_cmsdk_ahb_3), 0);
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irq_enable(DT_IRQ_PORT3_ALL);
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}
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#endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */
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