1f731c6c02
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
163 lines
4.4 KiB
C
163 lines
4.4 KiB
C
/*
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* Copyright (c) 2020 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NUVOTON_NPCX_SOC_CLOCK_H_
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#define _NUVOTON_NPCX_SOC_CLOCK_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Common clock control device name for all NPCX series */
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#define NPCX_CLK_CTRL_NAME DT_LABEL(DT_NODELABEL(pcc))
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/**
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* @brief NPCX clock configuration structure
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*
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* Used to indicate the device's clock bus type and corresponding PWDWN_CTL
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* register/bit to turn on/off its source clock.
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*/
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struct npcx_clk_cfg {
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uint16_t bus:8;
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uint16_t ctrl:5;
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uint16_t bit:3;
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};
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/*
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* NPCX7 and later series clock tree macros:
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* (Please refer Figure 58. for more information.)
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*
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* Suggestion:
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* - OSC_CLK >= 80MHz, XF_RANGE should be 1, else 0.
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* - CORE_CLK > 66MHz, AHB6DIV should be 1, else 0.
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* - CORE_CLK > 50MHz, FIUDIV should be 1, else 0.
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*/
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/* Target OSC_CLK freq */
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#define OSC_CLK CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC
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/* Core domain clock */
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#define CORE_CLK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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/* Low Frequency clock */
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#define LFCLK 32768
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/* Core clock prescaler */
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#define FPRED_VAL ((OSC_CLK / CORE_CLK) - 1)
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/* FMUL clock */
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#if (OSC_CLK >= 80000000)
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#define FMCLK (OSC_CLK / 2) /* FMUL clock = OSC_CLK/2 if OSC_CLK >= 80MHz */
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#else
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#define FMCLK OSC_CLK /* FMUL clock = OSC_CLK */
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#endif
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/* APBs source clock */
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#define APBSRC_CLK OSC_CLK
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/* APB1 clock divider, default value (APB1 clock = OSC_CLK/6) */
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#define APB1DIV_VAL (CONFIG_CLOCK_NPCX_APB1_PRESCALER - 1)
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/* APB2 clock divider, default value (APB2 clock = OSC_CLK/6) */
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#define APB2DIV_VAL (CONFIG_CLOCK_NPCX_APB2_PRESCALER - 1)
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/* APB3 clock divider, default value (APB3 clock = OSC_CLK/6) */
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#define APB3DIV_VAL (CONFIG_CLOCK_NPCX_APB3_PRESCALER - 1)
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/* AHB6 clock */
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#if (CORE_CLK > 66000000)
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#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 66MHz */
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#else
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#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
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#endif
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/* FIU clock divider */
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#if (CORE_CLK > 50000000)
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#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
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#else
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#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
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#endif
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/* Get APB clock freq */
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#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
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/*
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* Frequency multiplier M/N value definitions according to the requested
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* OSC_CLK (Unit:Hz).
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*/
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#if (OSC_CLK > 80000000)
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#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */
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#else
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#define HFCGN_VAL 0x02
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#endif
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#if (OSC_CLK == 100000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0xEC
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#elif (OSC_CLK == 90000000)
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#define HFCGMH_VAL 0x0A
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#define HFCGML_VAL 0xBA
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#elif (OSC_CLK == 80000000)
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#define HFCGMH_VAL 0x09
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#define HFCGML_VAL 0x89
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#elif (OSC_CLK == 66000000)
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#define HFCGMH_VAL 0x0F
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#define HFCGML_VAL 0xBC
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#elif (OSC_CLK == 50000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0xEC
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#elif (OSC_CLK == 48000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0x72
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#elif (OSC_CLK == 40000000)
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#define HFCGMH_VAL 0x09
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#define HFCGML_VAL 0x89
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#elif (OSC_CLK == 33000000)
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0xDE
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#elif (OSC_CLK == 30000000)
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#define HFCGMH_VAL 0x07
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#define HFCGML_VAL 0x27
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#elif (OSC_CLK == 26000000)
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#define HFCGMH_VAL 0x06
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#define HFCGML_VAL 0x33
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#else
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#error "Unsupported OSC_CLK Frequency"
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#endif
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/**
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* @brief Function to notify clock driver that backup the counter value of
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* low-frequency timer before ec entered deep idle state.
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*/
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void npcx_clock_capture_low_freq_timer(void);
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/**
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* @brief Function to notify clock driver that compensate the counter value of
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* system timer by low-frequency timer after ec left deep idle state.
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*
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*/
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void npcx_clock_compensate_system_timer(void);
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/**
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* @brief Function to get time ticks in system sleep/deep sleep state. The unit
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* is ticks.
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*
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*/
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uint64_t npcx_clock_get_sleep_ticks(void);
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/**
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* @brief Function to configure system sleep settings. After ec received "wfi"
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* instruction, ec will enter sleep/deep sleep state for better power
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* consumption.
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*
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* @param is_deep A boolean indicating ec enters deep sleep or sleep state
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* @param is_instant A boolean indicating 'Instant Wake-up' from deep idle is
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* enabled
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*/
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void npcx_clock_control_turn_on_system_sleep(bool is_deep, bool is_instant);
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/**
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* @brief Function to turn off system sleep mode.
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*/
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void npcx_clock_control_turn_off_system_sleep(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _NUVOTON_NPCX_SOC_CLOCK_H_ */
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