1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
63 lines
1.4 KiB
ArmAsm
63 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <linker/sections.h>
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#include <toolchain.h>
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#include <soc.h>
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/* Exports */
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GTEXT(_WdogInit)
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/* WDOG instance base address. */
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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#define WDOG_BASE 0x4002A000 /* WDOG0 */
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#else
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#define WDOG_BASE 0x41026000 /* WDOG1 */
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#endif
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/* Register offsets. */
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#define WDOG_CS_OFFSET 0x00
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#define WDOG_CNT_OFFSET 0x04
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#define WDOG_TOVAL_OFFSET 0x08
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/* Watchdog unlock key. */
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#define WDOG_CNT_UNLOCK 0xD928C520
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/* TOVAL must be set when disabling watchdog after reset. */
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#define WDOG_TOVAL_SET 0xFFFF
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/* Disable the WDOG_CS[EN] bit. */
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#define WDOG_CS_EN_DISABLED ~0x80
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/* Set WDOG_CS[UPDATE] bit. */
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#define WDOG_CS_UPDATE_ENABLED 0x20
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/*
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* Unlock and disable the watchdog, which is enabled by default.
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*/
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SECTION_FUNC(TEXT, _WdogInit)
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/* Disable interrupts if they're on. This is timing-sensitive code. */
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csrrc t0, mstatus, SOC_MSTATUS_IEN
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/* Get base address. */
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li t1, WDOG_BASE
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/* Unlock the watchdog. */
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li t2, WDOG_CNT_UNLOCK
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sw t2, WDOG_CNT_OFFSET(t1)
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/* Disable the watchdog. Allow updates later. */
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lw t2, WDOG_CS_OFFSET(t1)
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andi t2, t2, WDOG_CS_EN_DISABLED
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ori t2, t2, WDOG_CS_UPDATE_ENABLED
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sw t2, WDOG_CS_OFFSET(t1)
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/* This must also be done per reference manual. */
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li t2, WDOG_TOVAL_SET
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sw t2, WDOG_TOVAL_OFFSET(t1)
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/* Re-enable interrupts if they were disabled. */
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csrrs x0, mstatus, t0
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ret
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