1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_
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#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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/*
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* The following structure defines the list of registers that need to be
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* saved/restored when a cooperative context switch occurs.
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*/
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struct _callee_saved {
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u32_t sp; /* Stack pointer, (x2 register) */
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u32_t s0; /* saved register/frame pointer */
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u32_t s1; /* saved register */
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u32_t s2; /* saved register */
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u32_t s3; /* saved register */
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u32_t s4; /* saved register */
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u32_t s5; /* saved register */
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u32_t s6; /* saved register */
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u32_t s7; /* saved register */
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u32_t s8; /* saved register */
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u32_t s9; /* saved register */
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u32_t s10; /* saved register */
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u32_t s11; /* saved register */
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};
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typedef struct _callee_saved _callee_saved_t;
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struct _thread_arch {
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u32_t swap_return_value; /* Return value of z_swap() */
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ */
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