1c870f47b6
Configure Packet Trace Interface pinout on Series 2 boards. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
47 lines
739 B
Text
47 lines
739 B
Text
/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
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&pinctrl {
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itm_default: itm_default {
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group0 {
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pins = <GPIO_SWV_PA3>;
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drive-push-pull;
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output-high;
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};
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};
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i2c0_default: i2c0_default {
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group0 {
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pins = <I2C0_SCL_PC4>, <I2C0_SDA_PC5>;
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bias-pull-up;
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drive-open-drain;
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};
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};
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pti_default: pti_default {
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group0 {
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pins = <PTI_DOUT_PC6>, <PTI_DFRAME_PC7>;
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drive-push-pull;
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output-high;
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};
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};
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usart0_default: usart0_default {
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group0 {
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pins = <USART0_TX_PA5>;
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drive-push-pull;
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output-high;
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};
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group1 {
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pins = <USART0_RX_PA6>;
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input-enable;
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silabs,input-filter;
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};
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};
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};
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