174824f1cb
1. Move the GPIO mux setting to the soc layer. The GPIO MUX value may vary based on the SoC Family 2. Enable the digital input buffer if available Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
34 lines
530 B
C
34 lines
530 B
C
/*
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* Copyright (c) 2019 SEAL AG
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#include <zephyr/sys/util.h>
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#include <fsl_port.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include <fsl_common.h>
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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/* address bases */
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#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
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#define PORT_MUX_GPIO kPORT_MuxAsGpio /* GPIO setting for the Port Mux Register */
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#endif /* _SOC__H_ */
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