Use of Data Memory Barrier instruction with memory clobber in ARM Cortex M architectures is sufficient in the controller implementation to keep compiler data access instructions in order so that an ISR vectoring has memory accesses in the correct order as intented by design. Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no> |
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common | ||
controller | ||
host | ||
mesh | ||
services | ||
shell | ||
CMakeLists.txt | ||
Kconfig |