19d397d88e
This commit adds a second target for the stm32l562e_dk board. The non secure target can be configured for TFM IPC application. Signed-off-by: Yestin Sun <sunyi0804@gmail.com>
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295 lines
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.. _stm32l562e_dk_board:
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ST STM32L562E-DK Discovery
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##########################
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Overview
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********
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The STM32L562E-DK Discovery kit is designed as a complete demonstration and
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development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based
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STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of
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the STM32L562E-DK Discovery board:
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- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package
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- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel
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- USB Type-C |trade| Sink device FS
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- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface
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- SAI Audio CODEC
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- MEMS digital microphones
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- 512-Mbit Octal-SPI Flash memory
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- Bluetooth |reg| V4.1 Low Energy module
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- iNEMO 3D accelerometer and 3D gyroscope
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- Board connectors
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- STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors
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- Pmod |trade| expansion connector
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- Audio MEMS daughterboard expansion connector
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- ARDUINO |reg| Uno V3 expansion connector
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- Flexible power-supply options
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- ST-LINK
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- USB VBUS
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- external sources
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- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
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- mass storage
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- Virtual COM port
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- debug port
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- 2 user LEDs
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- User and reset push-buttons
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.. image:: img/stm32l562e_dk.jpg
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:width: 460px
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:align: center
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:height: 474px
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:alt: STM32L562E-DK Discovery
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More information about the board can be found at the `STM32L562E-DK Discovery website`_.
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Hardware
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********
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The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5
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Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core.
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They operate at a frequency of up to 110 MHz.
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- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
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- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
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- Performance benchmark:
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- 1.5 DMPIS/MHz (Drystone 2.1)
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- 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
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- Security
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- Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals
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- Flexible life cycle scheme with RDP (readout protection)
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- Root of trust thanks to unique boot entry and hide protection area (HDP)
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- Secure Firmware Installation thanks to embedded Root Secure Services
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- Secure Firmware Update support with TF-M
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- AES coprocessor
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- Public key accelerator
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- On-the-fly decryption of Octo-SPI external memories
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- HASH hardware accelerator
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- Active tamper and protection temperature, voltage and frequency attacks
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- True Random Number Generator NIST SP800-90B compliant
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- 96-bit unique ID
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- 512-byte One-Time Programmable for user data
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- Clock management:
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- 4 to 48 MHz crystal oscillator
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- 32 kHz crystal oscillator for RTC (LSE)
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- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
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- Internal low-power 32 kHz RC ( |plusminus| 5%)
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- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
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LSE (better than |plusminus| 0.25 % accuracy)
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- 3 PLLs for system clock, USB, audio, ADC
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- Power management
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- Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
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- Embedded SMPS step-down converter
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- External SMPS support
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- RTC with HW calendar, alarms and calibration
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- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
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- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors
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- Up to 16 timers and 2 watchdogs
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- 2x 16-bit advanced motor-control
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- 2x 32-bit and 5x 16-bit general purpose
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- 2x 16-bit basic
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- 3x low-power 16-bit timers (available in Stop mode)
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- 2x watchdogs
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- 2x SysTick timer
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- Memories
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- Up to 512 MB Flash, 2 banks read-while-write
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- 512 KB of SRAM including 64 KB with hardware parity check
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- External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories
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- OCTOSPI memory interface
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- Rich analog peripherals (independent supply)
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- 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
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- 2x 12-bit DAC, low-power sample and hold
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- 2x operational amplifiers with built-in PGA
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- 2x ultra-low-power comparators
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- 4x digital filters for sigma delta modulator
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- 19x communication interfaces
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- USB Type-C / USB power delivery controller
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- 2.0 full-speed crystal less solution, LPM and BCD
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- 2x SAIs (serial audio interface)
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- 4x I2C FM+(1 Mbit/s), SMBus/PMBus
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- 6x USARTs (ISO 7816, LIN, IrDA, modem)
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- 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode)
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- 1xFDCAN
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- 1xSDMMC interface
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- 2x 14 channel DMA controllers
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- CRC calculation unit
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- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
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More information about STM32L562QE can be found here:
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- `STM32L562QE on www.st.com`_
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- `STM32L562 reference manual`_
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Supported Features
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==================
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The Zephyr stm32l562e_dk board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| I2C | on-chip | i2c |
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+-----------+------------+-------------------------------------+
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| SPI | on-chip | spi |
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+-----------+------------+-------------------------------------+
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| TrustZone | on-chip | Trusted Firmware-M |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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The default configuration can be found in the defconfig file:
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``boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig``
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Connections and IOs
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===================
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STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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For mode details please refer to `STM32L562E-DK Discovery board User Manual`_.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- USART_1 TX/RX : PA9/PA10
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- I2C_1 SCL/SDA : PB6/PB7
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- SPI_1 SCK/MISO/MOSI : PG2/PG3/PG4 (BT SPI bus)
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- USER_PB : PC13
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- LD10 : PG12
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System Clock
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------------
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STM32L562E-DK System Clock could be driven by internal or external oscillator,
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as well as main PLL clock. By default System clock is driven by PLL clock at
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110MHz, driven by 4MHz medium speed internal oscillator.
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Serial Port
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-----------
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STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is
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assigned to USART1. Default settings are 115200 8N1.
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Programming and Debugging
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*************************
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Applications for the ``stm32l562e_dk`` board configuration can be built and
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flashed in the usual way (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Flashing
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========
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STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool
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interface. This interface is not yet supported by the openocd version.
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Instead, support can be enabled on pyocd by adding "pack" support with
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the following pyocd command:
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.. code-block:: console
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$ pyocd pack --update
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$ pyocd pack --install stm32l562qe
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STM32L562E-DK Discovery board includes an ST-LINK/V2-1 embedded debug tool
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interface. This interface is supported by the openocd version
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included in the Zephyr SDK since v0.9.2.
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Flashing an application to STM32L562E-DK Discovery
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--------------------------------------------------
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Connect the STM32L562E-DK Discovery to your host computer using the USB port.
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Then build and flash an application. Here is an example for the
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:ref:`hello_world` application.
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Run a serial host program to connect with your Nucleo board:
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.. code-block:: console
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$ minicom -D /dev/ttyACM0
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Then build and flash the application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: stm32l562e_dk
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:goals: build flash
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You should see the following message on the console:
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.. code-block:: console
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Hello World! stm32l562e_dk
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Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
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-----------------------------------------------------------------------------
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The TF-M integration sample :ref:`tfm_ipc` can be run on a STM32L562E-DK Discovery,
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using the ``stm32l562e_dk_ns`` target. When building a ``*_ns`` image with TF-M,
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a ``build/tfm/postbuild.sh`` bash script will be run automatically as a post-build step
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to make some required flash layout changes. The ``build/tfm/regression.sh`` script will
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need to be run to perform device initialization, and then run ``west flash --hex-file build/tfm_merged.hex``
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to flash the board.
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Check the ``build/tfm`` directory to ensure that the commands required by these scripts
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(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI``
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used for initialization is available in the PATH.
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Debugging
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=========
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You can debug an application in the usual way. Here is an example for the
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:ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: stm32l562e_dk
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:maybe-skip-config:
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:goals: debug
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.. _STM32L562E-DK Discovery website:
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https://www.st.com/en/evaluation-tools/stm32l562e-dk.html
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.. _STM32L562E-DK Discovery board User Manual:
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https://www.st.com/resource/en/user_manual/dm00635554.pdf
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.. _STM32L562QE on www.st.com:
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https://www.st.com/en/microcontrollers/stm32l562qe.html
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.. _STM32L562 reference manual:
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http://www.st.com/resource/en/reference_manual/DM00346336.pdf
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