Xtensa CPUs have incoherent L1 caches, which is deeply inconvenient
for SMP systems. But as a treatment for this, the ADSP memory map
contains the RAM twice, in separate 512MB regions that can be managed
separately by the Xtensa TLB/cacheattr mechanism. The low mapping is
set to bypass the cache where the high mapping is cached.
Set up linkage to use both as appropriate, then reassemble the final
sections to a contiguous region. Read-only areas (.text, .rodata) are
cached. Data sections are uncached by default, except for a special
".cache" section that may be used by higher level code to flag static
areas (e.g. stacks) which don't store multiprocessor-shared content.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
15e2117a0b