Andy Ross 14d008775a soc/intel_adsp: Clean up cache handling in MP startup ... There's no need to muck with the cache directly as long as we're careful about addressing the shared start record through an uncached volatile pointer. Correct a theoretical bug with the initial cache invalidate on the second CPU which was actually doing a flush (and thus potentially pushing things the boot ROM wrote into RAM now owned by the OS). Optimize memory layout a bit when using KERNEL_COHERENCE; we don't need a full cache line for the start record there as it's already in uncached memory. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2021-03-08 11:14:27 -05:00
..
cavs_v15	soc/intel_adsp: Move KERNEL_COHERENCE to cavs15	2021-02-11 14:47:40 -05:00
cavs_v18	cavs: (cosmetic) remove redundant LPRAM_* macros	2021-01-11 16:10:23 -05:00
cavs_v20	soc: intel_adsp: set trace size to non-zero	2021-01-12 20:53:40 -05:00
cavs_v25	soc: intel_adsp: set trace size to non-zero	2021-01-12 20:53:40 -05:00
common	soc/intel_adsp: Clean up cache handling in MP startup	2021-03-08 11:14:27 -05:00
CMakeLists.txt	xtensa: set toolchain variant per SoC	2020-12-20 14:30:50 -05:00
Kconfig	soc/intel_adsp: Move KERNEL_COHERENCE to cavs15	2021-02-11 14:47:40 -05:00
Kconfig.defconfig	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00
Kconfig.soc	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00