1462d3e972
Add timer support for RZ/A2M Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com> Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
101 lines
2.2 KiB
Text
101 lines
2.2 KiB
Text
/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <zephyr/dt-bindings/clock/renesas_rza2m_clock.h>
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/ {
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compatible = "renesas,r7s9210";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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osc: osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gic: interrupt-controller@e8221000 {
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compatible = "arm,gic-400", "arm,gic-v2", "arm,gic";
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#interrupt-cells = <4>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8221000 0x1000>,
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<0xe8222000 0x1000>;
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};
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ram: memory@80020000 {
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compatible = "mmio-sram";
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reg = <0x80020000 (DT_SIZE_M(4) - 0x20000)>;
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};
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cpg: clock-controller@fcfe0010 {
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compatible = "renesas,rza2m-cpg";
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reg = <0xfcfe0010 0x455>;
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#clock-cells = <1>;
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clocks = <&osc>;
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iclk: iclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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bclk: bclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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p1clk: p1clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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ostm0: timer@e803b000 {
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compatible = "renesas,rza2m-ostm";
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reg = <0xe803b000 0x30>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM0, RZA2M_CLK_P1C)>;
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status = "disabled";
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};
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ostm1: timer@e803c000 {
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compatible = "renesas,rza2m-ostm";
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reg = <0xe803c000 0x30>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM1, RZA2M_CLK_P1C)>;
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status = "disabled";
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};
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ostm2: timer@e803d000 {
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compatible = "renesas,rza2m-ostm";
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reg = <0xe803d000 0x30>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM2, RZA2M_CLK_P1C)>;
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status = "disabled";
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};
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};
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};
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