13e671e381
Fix the header guards for the ARM header files to reflect the new code location. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
115 lines
2.5 KiB
C
115 lines
2.5 KiB
C
/* ARM Cortex-M GCC specific public inline assembler functions and macros */
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/*
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* Copyright (c) 2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Either public functions or macros or invoked by public functions */
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_
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/*
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* The file must not be included directly
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* Include arch/cpu.h instead
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*/
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#ifndef _ASMLANGUAGE
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#include <zephyr/types.h>
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#include <arch/arm/aarch32/exc.h>
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#include <irq.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* On ARMv7-M and ARMv8-M Mainline CPUs, this function prevents regular
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* exceptions (i.e. with interrupt priority lower than or equal to
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* _EXC_IRQ_DEFAULT_PRIO) from interrupting the CPU. NMI, Faults, SVC,
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* and Zero Latency IRQs (if supported) may still interrupt the CPU.
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*
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* On ARMv6-M and ARMv8-M Baseline CPUs, this function reads the value of
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* PRIMASK which shows if interrupts are enabled, then disables all interrupts
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* except NMI.
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*/
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static ALWAYS_INLINE unsigned int arch_irq_lock(void)
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{
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unsigned int key;
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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__asm__ volatile("mrs %0, PRIMASK;"
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"cpsid i"
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: "=r" (key)
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:
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: "memory");
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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unsigned int tmp;
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__asm__ volatile(
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"mov %1, %2;"
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"mrs %0, BASEPRI;"
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"msr BASEPRI, %1;"
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"isb;"
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: "=r"(key), "=r"(tmp)
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: "i"(_EXC_IRQ_DEFAULT_PRIO)
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: "memory");
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#elif defined(CONFIG_ARMV7_R)
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__asm__ volatile("mrs %0, cpsr;"
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"cpsid i"
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: "=r" (key)
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:
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: "memory", "cc");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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return key;
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}
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/* On Cortex-M0/M0+, this enables all interrupts if they were not
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* previously disabled.
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*/
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static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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if (key) {
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return;
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}
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__asm__ volatile(
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"cpsie i;"
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"isb"
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: : : "memory");
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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__asm__ volatile(
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"msr BASEPRI, %0;"
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"isb;"
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: : "r"(key) : "memory");
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#elif defined(CONFIG_ARMV7_R)
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__asm__ volatile("msr cpsr_c, %0"
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:
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: "r" (key)
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: "memory", "cc");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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{
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/* This convention works for both PRIMASK and BASEPRI */
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return key == 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ASM_INLINE_GCC_H_ */
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