0f36f1a3ee
Restructure the Bosch M_CAN driver backend to use per-instance Message RAM configuration. This removes the need for a common, artificial "can" devicetree node for SoCs with multiple Bosch M_CAN-based CAN controllers and allows for per-instance configuration of the number of e.g. standard (11-bit) and extended (29-bit) filter elements. As part of the restructure, software handling of CAN filter flags was moved from per-flags bitfields to per-filter bitfields, solving an issue when using more than 32 standard (11-bit) filter elements or more than 16 extended (29-bit) filter elements. Fixes: #42030, #53417 Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
519 lines
12 KiB
Text
519 lines
12 KiB
Text
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/reset/stm32h5_reset.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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zephyr,entropy = &rng;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "st,stm32h7-hsi-clock";
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hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
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clock-frequency = <DT_FREQ_M(64)>;
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status = "disabled";
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};
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(4)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <2>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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/* The pll scheme is similar to stm32u5 */
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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pll2: pll2 {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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/* maximum erase time(ms) for a 8K sector */
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max-erase-time = <5>;
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};
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};
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rcc: rcc@44020c00 {
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compatible = "st,stm32u5-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x44020c00 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@44022000 {
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compatible = "st,stm32g0-exti", "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x44022000 0x400>;
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num-lines = <16>;
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interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
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<15 0>, <16 0>, <17 0>, <18 0>,
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<19 0>, <20 0>, <21 0>, <22 0>,
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<23 0>, <24 0>, <25 0>, <26 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2000>;
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gpioa: gpio@42020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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};
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gpiob: gpio@42020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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};
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gpioc: gpio@42020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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};
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gpiod: gpio@42020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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};
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gpioh: gpio@42021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
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};
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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interrupts = <58 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <59 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1L, 18U)>;
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interrupts = <60 0>;
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status = "disabled";
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};
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lpuart1: serial@44002400 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x44002400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
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resets = <&rctl STM32_RESET(APB3, 6U)>;
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interrupts = <63 0>;
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status = "disabled";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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dac1: dac@42028400 {
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compatible = "st,stm32-dac";
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reg = <0x42028400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000800>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc1: adc@42028000 {
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compatible = "st,stm32-adc";
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reg = <0x42028000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
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interrupts = <37 0>;
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status = "disabled";
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vref-mv = <3300>;
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#io-channel-cells = <1>;
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vbat-channel = <2>;
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temp-channel = <16>;
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vref-channel = <17>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 7 13 25 48 93 248 641>;
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};
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rtc: rtc@44007800 {
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compatible = "st,stm32-rtc";
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reg = <0x44007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
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prescaler = <32768>;
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
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resets = <&rctl STM32_RESET(APB2, 11U)>;
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interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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resets = <&rctl STM32_RESET(APB1L, 0U)>;
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interrupts = <45 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1L, 1U)>;
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interrupts = <46 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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resets = <&rctl STM32_RESET(APB1L, 4U)>;
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interrupts = <49 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1L, 5U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <51 0>, <52 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <53 0>, <54 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <55 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <56 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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interrupts = <57 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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status = "disabled";
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};
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can1: can@4000a400 {
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compatible = "st,stm32-fdcan";
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reg = <0x4000a400 0x400>, <0x4000ac00 0x350>;
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reg-names = "m_can", "message_ram";
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interrupts = <39 0>, <40 0>;
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interrupt-names = "LINE_0", "LINE_1";
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
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bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
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sjw = <1>;
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sample-point = <875>;
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sjw-data = <1>;
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sample-point-data = <875>;
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status = "disabled";
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};
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rng: rng@420c0800 {
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compatible = "st,stm32-rng";
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reg = <0x420c0800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
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interrupts = <114 0>;
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nist-config = <0xf00d00>;
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health-test-config = <0xaac7>;
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status = "disabled";
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};
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gpdma1: dma@40020000 {
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compatible = "st,stm32u5-dma";
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#dma-cells = <3>;
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reg = <0x40020000 0x1000>;
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interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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dma-channels = <8>;
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dma-requests = <140>;
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dma-offset = <0>;
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status = "disabled";
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};
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gpdma2: dma@40021000 {
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compatible = "st,stm32u5-dma";
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#dma-cells = <3>;
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reg = <0x40021000 0x1000>;
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interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
|
dma-channels = <8>;
|
|
dma-requests = <140>;
|
|
dma-offset = <8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal";
|
|
ts-cal1-addr = <0x08fff814>;
|
|
ts-cal2-addr = <0x08fff818>;
|
|
ts-cal1-temp = <30>;
|
|
ts-cal2-temp = <130>;
|
|
ts-cal-vrefanalog = <3300>;
|
|
ts-cal-resolution = <12>;
|
|
io-channels = <&adc1 16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vref: vref {
|
|
compatible = "st,stm32-vref";
|
|
vrefint-cal-addr = <0x08FFF810>;
|
|
vrefint-cal-mv = <3300>;
|
|
io-channels = <&adc1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vbat: vbat {
|
|
compatible = "st,stm32-vbat";
|
|
ratio = <4>;
|
|
io-channels = <&adc1 2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|