02e739873e
Add support for the memory controller by utilizing QSPIC2. The latter is capable to drive both NOR and PSRAM memory devices. For this to work, the RAM driving mode is enabled. Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
255 lines
8.2 KiB
C
255 lines
8.2 KiB
C
/*
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* Copyright (c) 2023 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_smartbond_nor_psram
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include <zephyr/irq.h>
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#include <DA1469xAB.h>
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#include <zephyr/pm/device.h>
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#include <da1469x_qspic.h>
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#include <da1469x_pd.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(smartbond_nor_psram, CONFIG_MEMC_LOG_LEVEL);
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#define CLK_AMBA_REG_SET_FIELD(_field, _var, _val) \
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((_var)) = \
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((_var) & ~(CRG_TOP_CLK_AMBA_REG_ ## _field ## _Msk)) | \
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(((_val) << CRG_TOP_CLK_AMBA_REG_ ## _field ## _Pos) & \
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CRG_TOP_CLK_AMBA_REG_ ## _field ## _Msk)
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#define QSPIC2_CTRLMODE_REG_SET_FIELD(_field, _var, _val) \
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((_var)) = \
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((_var) & ~(QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Msk)) | \
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(((_val) << QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Pos) & \
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QSPIC2_QSPIC2_CTRLMODE_REG_ ## _field ## _Msk)
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#define QSPIC2_BURSTCMDA_REG_SET_FIELD(_field, _var, _val) \
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((_var)) = \
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((_var) & ~(QSPIC2_QSPIC2_BURSTCMDA_REG_ ## _field ## _Msk)) | \
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(((_val) << QSPIC2_QSPIC2_BURSTCMDA_REG_ ## _field ## _Pos) & \
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QSPIC2_QSPIC2_BURSTCMDA_REG_ ## _field ## _Msk)
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#define QSPIC2_BURSTCMDB_REG_SET_FIELD(_field, _var, _val) \
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((_var)) = \
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((_var) & ~(QSPIC2_QSPIC2_BURSTCMDB_REG_ ## _field ## _Msk)) | \
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(((_val) << QSPIC2_QSPIC2_BURSTCMDB_REG_ ## _field ## _Pos) & \
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QSPIC2_QSPIC2_BURSTCMDB_REG_ ## _field ## _Msk)
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#define QSPIC2_AWRITECMD_REG_SET_FIELD(_field, _var, _val) \
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((_var)) = \
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((_var) & ~(QSPIC2_QSPIC2_AWRITECMD_REG_ ## _field ## _Msk)) | \
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(((_val) << QSPIC2_QSPIC2_AWRITECMD_REG_ ## _field ## _Pos) & \
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QSPIC2_QSPIC2_AWRITECMD_REG_ ## _field ## _Msk)
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static void memc_set_status(bool status, int clk_div)
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{
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unsigned int key;
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uint32_t clk_amba_reg;
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/* Clock AMBA register might be accessed by multiple driver classes */
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key = irq_lock();
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clk_amba_reg = CRG_TOP->CLK_AMBA_REG;
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if (status) {
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CLK_AMBA_REG_SET_FIELD(QSPI2_ENABLE, clk_amba_reg, 1);
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CLK_AMBA_REG_SET_FIELD(QSPI2_DIV, clk_amba_reg, clk_div);
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} else {
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CLK_AMBA_REG_SET_FIELD(QSPI2_ENABLE, clk_amba_reg, 0);
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}
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CRG_TOP->CLK_AMBA_REG = clk_amba_reg;
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irq_unlock(key);
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}
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static void memc_automode_configure(void)
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{
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uint32_t reg;
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reg = QSPIC2->QSPIC2_CTRLMODE_REG;
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_SRAM_EN, reg,
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DT_INST_PROP(0, is_ram));
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_USE_32BA, reg,
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DT_INST_ENUM_IDX(0, addr_range));
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_CLK_MD, reg,
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DT_INST_ENUM_IDX(0, clock_mode));
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_AUTO_MD, reg, 1);
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QSPIC2->QSPIC2_CTRLMODE_REG = reg;
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reg = QSPIC2->QSPIC2_BURSTCMDA_REG;
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_DMY_TX_MD, reg,
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DT_INST_ENUM_IDX(0, rx_dummy_mode));
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_ADR_TX_MD, reg,
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DT_INST_ENUM_IDX(0, rx_addr_mode));
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_INST_TX_MD, reg,
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DT_INST_ENUM_IDX(0, rx_inst_mode));
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#if DT_INST_PROP(0, extra_byte_enable)
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_EXT_TX_MD, reg,
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DT_INST_ENUM_IDX(0, rx_extra_mode));
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#endif
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_INST, reg,
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DT_INST_PROP(0, read_cmd));
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#if DT_INST_PROP(0, extra_byte_enable)
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QSPIC2_BURSTCMDA_REG_SET_FIELD(QSPIC_EXT_BYTE, reg,
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DT_INST_PROP(0, extra_byte));
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#endif
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QSPIC2->QSPIC2_BURSTCMDA_REG = reg;
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reg = QSPIC2->QSPIC2_BURSTCMDB_REG;
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QSPIC2_BURSTCMDB_REG_SET_FIELD(QSPIC_DMY_NUM, reg,
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DT_INST_ENUM_IDX(0, dummy_bytes_count));
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QSPIC2_BURSTCMDB_REG_SET_FIELD(QSPIC_DAT_RX_MD, reg,
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DT_INST_ENUM_IDX(0, rx_data_mode));
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QSPIC2_BURSTCMDB_REG_SET_FIELD(QSPIC_INST_MD, reg, 0);
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QSPIC2_BURSTCMDB_REG_SET_FIELD(QSPIC_EXT_BYTE_EN, reg,
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DT_INST_PROP(0, extra_byte_enable));
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QSPIC2->QSPIC2_BURSTCMDB_REG = reg;
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reg = QSPIC2->QSPIC2_AWRITECMD_REG;
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QSPIC2_AWRITECMD_REG_SET_FIELD(QSPIC_WR_DAT_TX_MD, reg,
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DT_INST_ENUM_IDX(0, tx_data_mode));
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QSPIC2_AWRITECMD_REG_SET_FIELD(QSPIC_WR_ADR_TX_MD, reg,
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DT_INST_ENUM_IDX(0, tx_addr_mode));
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QSPIC2_AWRITECMD_REG_SET_FIELD(QSPIC_WR_INST_TX_MD, reg,
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DT_INST_ENUM_IDX(0, tx_inst_mode));
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QSPIC2_AWRITECMD_REG_SET_FIELD(QSPIC_WR_INST, reg,
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DT_INST_PROP(0, write_cmd));
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QSPIC2->QSPIC2_AWRITECMD_REG = reg;
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}
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/* Read PSRAM/NOR device ID using JEDEC commands. */
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static bool memc_jedec_read_and_verify_id(QSPIC_TYPE qspi_id)
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{
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uint16_t device_density;
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bool ret = 0;
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qspi_memory_id_t memory_id;
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da1469x_qspi_memory_jedec_read_id(qspi_id, &memory_id);
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device_density = DT_INST_PROP(0, dev_density);
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ret |= !(memory_id.id == DT_INST_PROP(0, dev_id));
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ret |= !(memory_id.type == DT_INST_PROP(0, dev_type));
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ret |= !((memory_id.density & (device_density >> 8)) == (device_density & 0xFF));
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return ret;
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}
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static int memc_smartbond_init(const struct device *dev)
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{
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uint32_t qspic_ctrlmode_reg;
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/* First QSPI controller is enabled so registers can be accessed */
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memc_set_status(true, DT_INST_PROP_OR(0, clock_div, 0));
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/* Apply the min. required settings before performing any transaction in manual mode. */
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qspic_ctrlmode_reg = QSPIC2->QSPIC2_CTRLMODE_REG;
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_CLK_MD, qspic_ctrlmode_reg,
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DT_INST_ENUM_IDX(0, clock_mode));
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QSPIC2_CTRLMODE_REG_SET_FIELD(QSPIC_AUTO_MD, qspic_ctrlmode_reg, 0);
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QSPIC2->QSPIC2_CTRLMODE_REG = qspic_ctrlmode_reg;
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/* Reset PSRAM/NOR device using JDEC commands */
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da1469x_qspi_memory_jedec_reset(QSPIC2_ID);
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/* Wait till reset is completed */
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k_usleep(DT_INST_PROP(0, reset_delay_us));
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if (memc_jedec_read_and_verify_id(QSPIC2_ID)) {
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LOG_ERR("Device detection failed");
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memc_set_status(false, 0);
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return -EINVAL;
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}
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#if DT_INST_PROP(0, enter_qpi_mode)
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da1469x_qspi_enter_exit_qpi_mode(QSPIC2_ID, true, DT_INST_PROP(0, enter_qpi_cmd));
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#endif
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/* Should be called prior to switching to auto mode and when the quad bus is selected! */
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da1469x_qspi_set_bus_mode(QSPIC2_ID, QSPI_BUS_MODE_QUAD);
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#if CONFIG_PM_DEVICE_RUNTIME
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/*
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* Turn off the controller to minimize power consumption. Application is responsible to
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* configure/de-configure the controller before interacting with the memory.
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*/
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memc_set_status(false, 0);
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/* Make sure device is marked as suspended */
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pm_device_init_suspended(dev);
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return pm_device_runtime_enable(dev);
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#else
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da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
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/* From this point onwards memory device should be seen as memory mapped device. */
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memc_automode_configure();
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#endif
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return 0;
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}
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#ifdef CONFIG_PM_DEVICE
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static int memc_smartbond_pm_action(const struct device *dev, enum pm_device_action action)
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{
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switch (action) {
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case PM_DEVICE_ACTION_SUSPEND:
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/*
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* CLK_AMBA_REG, that controlls QSPIC2, is retained during sleep
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* (resides in PD_AON). However, unused blocks should be disabled
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* to minimize power consumption at sleep.
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*/
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memc_set_status(false, 0);
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da1469x_pd_release(MCU_PD_DOMAIN_SYS);
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break;
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case PM_DEVICE_ACTION_RESUME:
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/*
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* Mainly, required when in PM runtime mode. When in PM static mode,
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* the device will block till an ongoing/pending AMBA bus transfer
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* completes.
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*/
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da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
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/*
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* QSPIC2 is powered by PD_SYS which is turned off during sleep and
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* so QSPIC2 auto mode re-initialization is required.
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*
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* XXX: It's assumed that memory device's power rail, that should
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* be 1V8P, is not turned off and so the device itsef does not
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* require re-initialization. Revisit this part if power settings
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* are changed in the future, that should include:
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*
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* 1. Powering off the memory device by turning off 1V8P
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* (valid for FLASH/PSRAM).
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* 2. Powering down the memory device so it enters the suspend/low-power
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* state during sleep (valid for FLASH/NOR devices).
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*/
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memc_set_status(true, DT_INST_PROP_OR(0, clock_div, 0));
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memc_automode_configure();
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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#endif
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#define SMARTBOND_MEMC_INIT(inst) \
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BUILD_ASSERT(inst == 0, "multiple instances are not permitted"); \
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BUILD_ASSERT(DT_INST_PROP(inst, is_ram), \
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"current driver version suports only PSRAM devices"); \
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\
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PM_DEVICE_DT_INST_DEFINE(inst, memc_smartbond_pm_action); \
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\
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DEVICE_DT_INST_DEFINE(inst, memc_smartbond_init, PM_DEVICE_DT_INST_GET(inst), \
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NULL, NULL, \
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POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY, NULL);
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DT_INST_FOREACH_STATUS_OKAY(SMARTBOND_MEMC_INIT)
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