564f59060c
In SMP, the system timer is used for timeslicing on auxiliary CPUs, but the base system timekeeping via _nano_sys_clock_tick_announce() is still done on CPU0 only (because the framework isn't prepared for asynchronous notification yet). Skip processing on CPU1+. Also, due to a hardware interaction* that is difficult to work around, timer initialization on the auxiliary CPUs is done at the very end of the CPU bringup, just before the swap into the scheduler. A smp_timer_init() API has been added for this purpose. * On ESP-32, enabling the timer seems to result in a near-synchronous interrupt being delivered despite my best attempts to keep it masked, then blowing things up because the CPU record isn't set up to handle it yet. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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| .. | ||
| altera_avalon_timer_hal.c | ||
| arcv2_timer0.c | ||
| CMakeLists.txt | ||
| cortex_m_systick.c | ||
| hpet.c | ||
| Kconfig | ||
| loapic_timer.c | ||
| native_posix_timer.c | ||
| nrf_rtc_timer.c | ||
| pulpino_timer.c | ||
| riscv_machine_timer.c | ||
| sys_clock_init.c | ||
| xtensa_sys_timer.c | ||