e1a90583d4
Align stm32f1xx series clock driver to other parts of stm32 family. Driver support both Connectivity and Density lines of stm32f1 series, that are based on different Reset and Clock Control architectures. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "stm32_ll_clock.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/*
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* Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
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* STM32F107xx).
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* Both flags are defined in STM32Cube LL API. Keep only the selected one.
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*/
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#ifdef CONFIG_CLOCK_STM32_PLL_SRC_PLL2
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#undef RCC_PREDIV1_SOURCE_HSE
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#else
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#undef RCC_PREDIV1_SOURCE_PLL2
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_PLL2 */
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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/*
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* PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*
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* PLLMUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 9 -> LL_RCC_PLL_MUL_9 -> 0x001C0000
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* 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMULL_Pos);
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#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
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/* PLL prediv */
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#ifdef CONFIG_CLOCK_STM32_PLL_XTPRE
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE/2 used as PLL source
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*/
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pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
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#else
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE used as direct PLL source
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*/
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pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
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#endif /* CONFIG_CLOCK_STM32_PLL_XTPRE */
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#else
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/*
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* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1;
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#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Nothing for now */
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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