aec9a8c4be
Before introducing the code for ARM64 (AArch64) we need to relocate the current ARM code to a new AArch32 sub-directory. For now we can assume that no code is shared between ARM and ARM64. There are no functional changes. The code is moved to the new location and the file paths are fixed to reflect this change. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h>
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static const struct nxp_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("DEBUGGER_0",
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0,
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0xFFFFFFFF,
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REGION_DEBUG_ATTR),
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/* The NXP MPU does not give precedence to memory regions like the ARM
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* MPU, which means that if one region grants access then another
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* region cannot revoke access. If an application enables hardware
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* stack protection, we need to disable supervisor writes from the core
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* to the stack guard region. As a result, we cannot have a single
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* background region that enables supervisor read/write access from the
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* core to the entire address space, and instead define two background
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* regions that together cover the entire address space except for
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* SRAM.
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*/
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/* Region 1 */
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MPU_REGION_ENTRY("BACKGROUND_0",
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0,
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CONFIG_SRAM_BASE_ADDRESS-1,
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REGION_BACKGROUND_ATTR),
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/* Region 2 */
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MPU_REGION_ENTRY("BACKGROUND_1",
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CONFIG_SRAM_BASE_ADDRESS +
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(CONFIG_SRAM_SIZE * 1024),
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0xFFFFFFFF,
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REGION_BACKGROUND_ATTR),
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/* Region 3 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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(CONFIG_FLASH_BASE_ADDRESS +
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(CONFIG_FLASH_SIZE * 1024) - 1),
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REGION_FLASH_ATTR),
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/* Region 4 */
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MPU_REGION_ENTRY("RAM_U_0",
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CONFIG_SRAM_BASE_ADDRESS,
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(CONFIG_SRAM_BASE_ADDRESS +
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(CONFIG_SRAM_SIZE * 1024) - 1),
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REGION_RAM_ATTR),
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};
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const struct nxp_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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.sram_region = 4,
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};
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