a1b77fd589
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
238 lines
6.6 KiB
C
238 lines
6.6 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INC_SOC_H
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#define __INC_SOC_H
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/* macros related to interrupt handling */
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#define XTENSA_IRQ_NUM_SHIFT 0
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#define CAVS_IRQ_NUM_SHIFT 8
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#define INTR_CNTL_IRQ_NUM_SHIFT 16
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#define XTENSA_IRQ_NUM_MASK 0xff
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#define CAVS_IRQ_NUM_MASK 0xff
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#define INTR_CNTL_IRQ_NUM_MASK 0xff
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/*
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* IRQs are mapped on 3 levels. 4th level is left 0x00.
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*
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* 1. Peripheral Register bit offset.
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* 2. CAVS logic bit offset.
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* 3. Core interrupt number.
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*/
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#define XTENSA_IRQ_NUMBER(_irq) \
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((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
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#define CAVS_IRQ_NUMBER(_irq) \
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(((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1)
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#define INTR_CNTL_IRQ_NUM(_irq) \
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(((_irq >> INTR_CNTL_IRQ_NUM_SHIFT) & INTR_CNTL_IRQ_NUM_MASK) - 1)
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/* Macro that aggregates the tri-level interrupt into an IRQ number */
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#define SOC_AGGREGATE_IRQ(ictl_irq, cavs_irq, core_irq) \
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(((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \
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(((cavs_irq) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) | \
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(((ictl_irq) & INTR_CNTL_IRQ_NUM_MASK) << INTR_CNTL_IRQ_NUM_SHIFT))
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#define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc))
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#define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x)
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#define IOAPIC_EDGE 0
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#define IOAPIC_HIGH 0
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/* DW interrupt controller */
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#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_IRQN(DT_INST(0, snps_designware_intc)))
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#define DW_ICTL_NUM_IRQS 9
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/* GPIO */
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#define GPIO_DW_PORT_0_INT_MASK 0
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#define DMA_HANDSHAKE_DMIC_RXA 0
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#define DMA_HANDSHAKE_DMIC_RXB 1
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#define DMA_HANDSHAKE_SSP0_TX 2
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#define DMA_HANDSHAKE_SSP0_RX 3
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#define DMA_HANDSHAKE_SSP1_TX 4
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#define DMA_HANDSHAKE_SSP1_RX 5
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#define DMA_HANDSHAKE_SSP2_TX 6
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#define DMA_HANDSHAKE_SSP2_RX 7
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#define DMA_HANDSHAKE_SSP3_TX 8
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#define DMA_HANDSHAKE_SSP3_RX 9
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/* DMA Channel Allocation
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* FIXME: I2S Driver assigns channel in Kconfig.
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* Perhaps DTS is a better option
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*/
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#define DMIC_DMA_DEV_NAME CONFIG_DMA_0_NAME
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#define DMA_CHANNEL_DMIC_RXA 0
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#define DMA_CHANNEL_DMIC_RXB 1
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/* I2S */
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#define I2S_CAVS_IRQ(i2s_num) \
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SOC_AGGREGATE_IRQ(0, (i2s_num) + 1, CAVS_L2_AGG_INT_LEVEL5)
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#define I2S0_CAVS_IRQ I2S_CAVS_IRQ(0)
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#define I2S1_CAVS_IRQ I2S_CAVS_IRQ(1)
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#define I2S2_CAVS_IRQ I2S_CAVS_IRQ(2)
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#define I2S3_CAVS_IRQ I2S_CAVS_IRQ(3)
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#define SSP_SIZE 0x0000200
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#define SSP_BASE(x) (0x00077000 + (x) * SSP_SIZE)
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#define SSP_MN_DIV_SIZE (8)
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#define SSP_MN_DIV_BASE(x) \
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(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
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/* MCLK control */
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#define SOC_MCLK_DIV_CTRL_BASE 0x78C00
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#define SOC_NUM_MCLK_OUTPUTS 2
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#define SOC_MDIVCTRL_MCLK_OUT_EN(mclk) BIT(mclk)
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#define SOC_MDIVXR_SET_DIVIDER_BYPASS BIT_MASK(12)
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struct soc_mclk_control_regs {
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uint32_t mdivctrl;
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uint32_t reserved[31];
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uint32_t mdivxr[SOC_NUM_MCLK_OUTPUTS];
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};
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#define PDM_BASE 0x00010000
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#define SOC_NUM_LPGPDMAC 3
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#define SOC_NUM_CHANNELS_IN_DMAC 8
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/* DSP Wall Clock Timers (0 and 1) */
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#define DSP_WCT_IRQ(x) \
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SOC_AGGREGATE_IRQ(0, (23 + x), CAVS_L2_AGG_INT_LEVEL2)
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#define DSP_WCT_CS_TA(x) BIT(x)
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#define DSP_WCT_CS_TT(x) BIT(4 + x)
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/* SOC Resource Allocation Registers */
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#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
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/* bit field definition for LP GPDMA ownership register */
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#define SOC_LPGPDMAC_OWNER_DSP \
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(BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC))
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#define SOC_NUM_I2S_INSTANCES 4
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/* bit field definition for IO peripheral ownership register */
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#define SOC_DSPIOP_I2S_OWNSEL_DSP \
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(BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8)
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#define SOC_DSPIOP_DMIC_OWNSEL_DSP BIT(0)
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/* bit field definition for general ownership register */
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#define SOC_GENO_TIMESTAMP_OWNER_DSP BIT(2)
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#define SOC_GENO_MNDIV_OWNER_DSP BIT(1)
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struct soc_resource_alloc_regs {
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union {
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uint16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
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uint16_t reserved[4];
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};
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uint32_t dspiopo;
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uint32_t geno;
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};
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/* L2 Local Memory Registers */
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#define SOC_L2RAM_LOCAL_MEM_REG_BASE 0x00071D00
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#define SOC_L2RAM_LOCAL_MEM_REG_LSPGCTL \
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(SOC_L2RAM_LOCAL_MEM_REG_BASE + 0x50)
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/* DMIC SHIM Registers */
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#define SOC_DMIC_SHIM_REG_BASE 0x00071E80
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#define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0)
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#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
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struct soc_dmic_shim_regs {
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uint32_t dmiclcap;
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uint32_t dmiclctl;
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};
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/* SOC DSP SHIM Registers */
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#define SOC_DSP_SHIM_REG_BASE 0x00071F00
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/* SOC DSP SHIM Register - Clock Control */
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#define SOC_CLKCTL_REQ_FAST_CLK BIT(31)
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#define SOC_CLKCTL_REQ_SLOW_CLK BIT(30)
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#define SOC_CLKCTL_OCS_FAST_CLK BIT(2)
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/* SOC DSP SHIM Register - Power Control */
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#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0 BIT(0)
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#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
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struct soc_dsp_shim_regs {
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uint32_t reserved[8];
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union {
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struct {
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uint32_t walclk32_lo;
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uint32_t walclk32_hi;
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};
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uint64_t walclk;
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};
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uint32_t dspwctcs;
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uint32_t reserved1[1];
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union {
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struct {
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uint32_t dspwct0c32_lo;
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uint32_t dspwct0c32_hi;
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};
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uint64_t dspwct0c;
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};
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union {
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struct {
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uint32_t dspwct1c32_lo;
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uint32_t dspwct1c32_hi;
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};
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uint64_t dspwct1c;
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};
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uint32_t reserved2[14];
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uint32_t clkctl;
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uint32_t clksts;
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uint32_t reserved3[4];
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uint16_t pwrctl;
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uint16_t pwrsts;
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uint32_t lpsctl;
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uint32_t lpsdmas0;
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uint32_t lpsdmas1;
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uint32_t reserved4[22];
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};
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/* Global Control registers */
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#define SOC_S1000_GLB_CTRL_BASE (0x00081C00)
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#define SOC_GNA_POWER_CONTROL_SPA (BIT(0))
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#define SOC_GNA_POWER_CONTROL_CPA (BIT(8))
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#define SOC_GNA_POWER_CONTROL_CLK_EN (BIT(16))
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#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CRST BIT(1)
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#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CSTALL BIT(9)
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#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_SPA BIT(17)
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#define SOC_S1000_GLB_CTRL_DSP1_PWRCTL_CPA BIT(25)
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#define SOC_S1000_STRAP_REF_CLK (BIT_MASK(2) << 3)
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#define SOC_S1000_STRAP_REF_CLK_38P4 (0 << 3)
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#define SOC_S1000_STRAP_REF_CLK_19P2 (1 << 3)
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#define SOC_S1000_STRAP_REF_CLK_24P576 (2 << 3)
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struct soc_global_regs {
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uint32_t reserved1[5];
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uint32_t cavs_dsp1power_control;
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uint32_t reserved2[2];
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uint32_t gna_power_control;
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uint32_t reserved3[7];
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uint32_t straps;
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};
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/* macros for data cache operations */
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#define SOC_DCACHE_FLUSH(addr, size) \
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xthal_dcache_region_writeback((addr), (size))
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#define SOC_DCACHE_INVALIDATE(addr, size) \
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xthal_dcache_region_invalidate((addr), (size))
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extern void z_soc_irq_enable(uint32_t irq);
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extern void z_soc_irq_disable(uint32_t irq);
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extern int z_soc_irq_is_enabled(unsigned int irq);
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extern uint32_t soc_get_ref_clk_freq(void);
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#endif /* __INC_SOC_H */
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