4192254ef2
Added properties to support the core interrupt controller on the NIOS2 cpu cores and enable that support for the NS16550 UART. We rename some compatibles so that the cpu core compatibles is unique. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
58 lines
981 B
Plaintext
58 lines
981 B
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include "skeleton.dtsi"
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "altera,nios2f";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x00 0xb8000>;
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};
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sram0: memory@400000 {
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compatible = "mmio-sram";
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reg = <0x400000 0x20000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&cpu>;
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ranges;
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uart0: uart@f0008000 {
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compatible = "ns16550";
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reg = <0xf0008000 0x400>;
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clock-frequency = <50000000>;
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interrupts = <1 0>;
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label = "UART_0";
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status = "disabled";
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};
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i2c0: i2c@100200 {
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compatible = "nios2,i2c";
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clock-frequency = <I2C_BITRATE_ULTRA>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x100200 0x400>;
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label = "I2C_0";
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};
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};
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};
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