4192254ef2
Added properties to support the core interrupt controller on the NIOS2 cpu cores and enable that support for the NS16550 UART. We rename some compatibles so that the cpu core compatibles is unique. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
55 lines
915 B
Plaintext
55 lines
915 B
Plaintext
/* SPDX-License-Identifier: Apache-2.0 */
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#include "skeleton.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "qemu,nios2-zephyr";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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flash0: flash@420000 {
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compatible = "soc-nv-flash";
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reg = <0x420000 0x20000>;
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};
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sram0: memory@400000 {
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compatible = "mmio-sram";
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reg = <0x400000 0x20000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&cpu>;
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ranges;
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jtag_uart: uart@201000 {
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compatible = "altera,jtag-uart";
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reg = <0x201000 0x400>;
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label = "jtag_uart0";
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status = "disabled";
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};
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ns16550_uart: uart@440000 {
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compatible = "ns16550";
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reg = <0x440000 0x400>;
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interrupts = <1>;
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clock-frequency = <50000000>;
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label = "UART_0";
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status = "disabled";
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};
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};
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};
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