8922afb0f8
On power-on boot-ROM is mapped to address 0 in HSDK board. Normally later when U-Boot gets started by boot-ROM we change mappings so that real DDR is mapped to entire address space including 0: https://elixir.bootlin.com/u-boot/latest/source/board/synopsys/hsdk/hsdk.c#L474 But if U-Boot is not started (which is controlled by the BIM dip-switch on the board) boot-ROM remains mapped to 0, and essentially any attempt to write to that location fails, thus we cannot upload contents of our target Elf there even with JTAG. The next logical option is to use beginning of the non-translated memory region 0x8000_0000 which we typically use for loading U-Boot & Linux kernel on ARC boards. But in case of HSDK we have DCCM (Data Closely-Coupled MEmory - fast on-chip SRAM) mapped there and since we cannot execute code from DCCM we need to skip that region as well which gives us the next option being 0x9000_0000 . That's because DCCM owns entire 256 MiB "aperture" even though it may have much smaller size up-to 8 MiB. We are mapping only 5 apertures because the last two (0xe000_0000-0xffff_ffff) are used for peripherals and AXI. Signed-off-by: Evgeniy Didin <didin@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
190 lines
3.5 KiB
Plaintext
190 lines
3.5 KiB
Plaintext
/*
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* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <3>;
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};
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};
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intc: arcv2-intc {
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compatible = "snps,arcv2-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&idu_intc>;
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ranges;
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ddr0: memory@90000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90000000 0x50000000>;
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};
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uart0: uart@f0005000 {
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compatible = "ns16550";
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clock-frequency = <33333333>;
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reg = <0xf0005000 0x1000>;
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label = "UART_0";
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interrupts = <30 1>;
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};
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uart1: uart@f0026000{
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compatible = "ns16550";
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clock-frequency = <33333333>;
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reg = <0xf0026000 0x1000>;
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label = "UART_1";
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interrupts = <46 1>;
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status = "disabled";
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};
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uart2: uart@f0027000 {
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compatible = "ns16550";
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clock-frequency = <33333333>;
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reg = <0xf0027000 0x1000>;
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label = "UART_2";
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interrupts = <47 1>;
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status = "disabled";
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};
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uart3: uart@f0028000 {
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compatible = "ns16550";
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clock-frequency = <33333333>;
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reg = <0xf0028000 0x1000>;
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label = "UART_3";
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interrupts = <48 1>;
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status = "disabled";
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};
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gpio0: gpio@f0003000 {
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compatible = "snps,designware-gpio";
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reg = <0xf0003000 0x1000>;
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bits = <24>;
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label = "GPIO_0";
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interrupt-parent = <&idu_intc>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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i2c0: i2c@f0023000 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0023000 0x1000>;
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interrupts = <43 1>;
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label = "I2C_0";
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status = "disabled";
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};
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i2c1: i2c@f0024000 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0024000 0x1000>;
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interrupts = <44 1>;
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label = "I2C_1";
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status = "disabled";
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};
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i2c2: i2c@f0025000 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0025000 0x1000>;
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interrupts = <45 1>;
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label = "I2C_2";
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status = "disabled";
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};
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spi0: spi@f0020000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0020000 0x1000>;
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interrupts = <40 1>;
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label = "SPI_0";
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status = "disabled";
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};
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spi1: spi@f0021000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0021000 0x1000>;
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interrupts = <41 1>;
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label = "SPI_1";
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status = "disabled";
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};
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spi2: spi@f0022000 {
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compatible = "snps,designware-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xf0022000 0x1000>;
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interrupts = <42 1>;
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label = "SPI_2";
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status = "disabled";
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};
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};
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};
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