a1b77fd589
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
214 lines
6.2 KiB
C
214 lines
6.2 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Designware USB device controller driver private definitions
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*
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* This file contains the Designware USB device controller driver private
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* definitions.
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*/
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#ifndef ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_
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#define ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_
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#include <sys/util.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Number of USB controllers */
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enum USB_DW_N { USB_DW_0 = 0, USB_DW_NUM };
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/* USB IN EP index */
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enum usb_dw_in_ep_idx {
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USB_DW_IN_EP_0 = 0,
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USB_DW_IN_EP_1,
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USB_DW_IN_EP_2,
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USB_DW_IN_EP_3,
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USB_DW_IN_EP_4,
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USB_DW_IN_EP_5,
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USB_DW_IN_EP_NUM
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};
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/* USB OUT EP index */
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enum usb_dw_out_ep_idx {
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USB_DW_OUT_EP_0 = 0,
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USB_DW_OUT_EP_1,
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USB_DW_OUT_EP_2,
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USB_DW_OUT_EP_3,
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USB_DW_OUT_EP_NUM
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};
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/* USB IN EP Register block type */
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struct usb_dw_in_ep_reg {
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volatile uint32_t diepctl;
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uint32_t reserved;
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volatile uint32_t diepint;
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uint32_t reserved1;
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volatile uint32_t dieptsiz;
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volatile uint32_t diepdma;
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volatile uint32_t dtxfsts;
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uint32_t reserved2;
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};
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/* USB OUT EP Register block type */
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struct usb_dw_out_ep_reg {
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volatile uint32_t doepctl;
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uint32_t reserved;
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volatile uint32_t doepint;
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uint32_t reserved1;
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volatile uint32_t doeptsiz;
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volatile uint32_t doepdma;
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uint32_t reserved2;
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uint32_t reserved3;
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};
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/* USB Register block type */
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struct usb_dw_reg {
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volatile uint32_t gotgctl;
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volatile uint32_t gotgint;
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volatile uint32_t gahbcfg;
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volatile uint32_t gusbcfg;
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volatile uint32_t grstctl;
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volatile uint32_t gintsts;
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volatile uint32_t gintmsk;
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volatile uint32_t grxstsr;
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volatile uint32_t grxstsp;
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volatile uint32_t grxfsiz;
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volatile uint32_t gnptxfsiz;
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uint32_t reserved[5];
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volatile uint32_t gsnpsid;
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volatile uint32_t ghwcfg1;
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volatile uint32_t ghwcfg2;
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volatile uint32_t ghwcfg3;
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volatile uint32_t ghwcfg4;
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volatile uint32_t gdfifocfg;
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uint32_t reserved1[43];
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volatile uint32_t dieptxf1;
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volatile uint32_t dieptxf2;
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volatile uint32_t dieptxf3;
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volatile uint32_t dieptxf4;
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volatile uint32_t dieptxf5;
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uint32_t reserved2[442];
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volatile uint32_t dcfg;
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volatile uint32_t dctl;
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volatile uint32_t dsts;
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uint32_t reserved3;
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volatile uint32_t diepmsk;
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volatile uint32_t doepmsk;
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volatile uint32_t daint;
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volatile uint32_t daintmsk;
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uint32_t reserved4[2];
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volatile uint32_t dvbusdis;
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volatile uint32_t dvbuspulse;
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volatile uint32_t dthrctl;
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volatile uint32_t diepempmsk;
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uint32_t reserved5[50];
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struct usb_dw_in_ep_reg in_ep_reg[USB_DW_IN_EP_NUM];
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uint32_t reserved6[80];
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struct usb_dw_out_ep_reg out_ep_reg[USB_DW_OUT_EP_NUM];
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};
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/* USB register offsets and masks */
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#define USB_DW_HWCFG4_DEDFIFOMODE BIT(25)
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#define USB_DW_GUSBCFG_PHY_IF_MASK BIT(3)
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#define USB_DW_GUSBCFG_PHY_IF_8_BIT (0)
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#define USB_DW_GUSBCFG_PHY_IF_16_BIT (1<<3)
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#define USB_DW_GRSTCTL_AHB_IDLE BIT(31)
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#define USB_DW_GRSTCTL_TX_FNUM_OFFSET (6)
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#define USB_DW_GRSTCTL_TX_FFLSH BIT(5)
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#define USB_DW_GRSTCTL_C_SFT_RST BIT(0)
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#define USB_DW_GAHBCFG_DMA_EN BIT(5)
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#define USB_DW_GAHBCFG_GLB_INTR_MASK BIT(0)
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#define USB_DW_DCTL_SFT_DISCON BIT(1)
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#define USB_DW_GINTSTS_WK_UP_INT BIT(31)
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#define USB_DW_GINTSTS_OEP_INT BIT(19)
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#define USB_DW_GINTSTS_IEP_INT BIT(18)
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#define USB_DW_GINTSTS_ENUM_DONE BIT(13)
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#define USB_DW_GINTSTS_USB_RST BIT(12)
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#define USB_DW_GINTSTS_USB_SUSP BIT(11)
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#define USB_DW_GINTSTS_RX_FLVL BIT(4)
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#define USB_DW_GINTSTS_OTG_INT BIT(2)
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#define USB_DW_DCFG_DEV_SPD_USB2_HS (0)
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#define USB_DW_DCFG_DEV_SPD_USB2_FS (0x1)
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#define USB_DW_DCFG_DEV_SPD_LS (0x2)
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#define USB_DW_DCFG_DEV_SPD_FS (0x3)
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#define USB_DW_DCFG_DEV_ADDR_MASK (0x7F << 4)
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#define USB_DW_DCFG_DEV_ADDR_OFFSET (4)
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#define USB_DW_DAINT_IN_EP_INT(ep) (1 << (ep))
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#define USB_DW_DAINT_OUT_EP_INT(ep) (0x10000 << (ep))
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#define USB_DW_DEPCTL_EP_ENA BIT(31)
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#define USB_DW_DEPCTL_EP_DIS BIT(30)
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#define USB_DW_DEPCTL_SETDOPID BIT(28)
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#define USB_DW_DEPCTL_SNAK BIT(27)
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#define USB_DW_DEPCTL_CNAK BIT(26)
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#define USB_DW_DEPCTL_STALL BIT(21)
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#define USB_DW_DEPCTL_TXFNUM_OFFSET (22)
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#define USB_DW_DEPCTL_TXFNUM_MASK (0xf << 22)
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#define USB_DW_DEPCTL_EP_TYPE_MASK (0x3 << 18)
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#define USB_DW_DEPCTL_EP_TYPE_OFFSET (18)
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#define USB_DW_DEPCTL_EP_TYPE_CONTROL (0)
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#define USB_DW_DEPCTL_EP_TYPE_ISO (0x1)
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#define USB_DW_DEPCTL_EP_TYPE_BULK (0x2)
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#define USB_DW_DEPCTL_EP_TYPE_INTERRUPT (0x3)
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#define USB_DW_DEPCTL_USB_ACT_EP BIT(15)
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#define USB_DW_DEPCTL0_MSP_MASK (0x3)
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#define USB_DW_DEPCTL0_MSP_8 (0x3)
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#define USB_DW_DEPCTL0_MSP_16 (0x2)
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#define USB_DW_DEPCTL0_MSP_32 (0x1)
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#define USB_DW_DEPCTL0_MSP_64 (0)
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#define USB_DW_DEPCTLn_MSP_MASK (0x3FF)
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#define USB_DW_DEPCTL_MSP_OFFSET (0)
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#define USB_DW_DOEPTSIZ_SUP_CNT_MASK (0x3 << 29)
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#define USB_DW_DOEPTSIZ_SUP_CNT_OFFSET (29)
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#define USB_DW_DOEPTSIZ0_PKT_CNT_MASK (0x1 << 19)
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#define USB_DW_DOEPTSIZn_PKT_CNT_MASK (0x3FF << 19)
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#define USB_DW_DIEPTSIZ0_PKT_CNT_MASK (0x3 << 19)
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#define USB_DW_DIEPTSIZn_PKT_CNT_MASK (0x3FF << 19)
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#define USB_DW_DEPTSIZ_PKT_CNT_OFFSET (19)
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#define USB_DW_DEPTSIZ0_XFER_SIZE_MASK (0x7F)
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#define USB_DW_DEPTSIZn_XFER_SIZE_MASK (0x7FFFF)
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#define USB_DW_DEPTSIZ_XFER_SIZE_OFFSET (0)
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#define USB_DW_DIEPINT_XFER_COMPL BIT(0)
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#define USB_DW_DIEPINT_TX_FEMP BIT(7)
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#define USB_DW_DIEPINT_XFER_COMPL BIT(0)
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#define USB_DW_DOEPINT_SET_UP BIT(3)
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#define USB_DW_DOEPINT_XFER_COMPL BIT(0)
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#define USB_DW_DSTS_ENUM_SPD_MASK (0x3)
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#define USB_DW_DSTS_ENUM_SPD_OFFSET (1)
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#define USB_DW_DSTS_ENUM_LS (2)
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#define USB_DW_DSTS_ENUM_FS (3)
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#define USB_DW_GRXSTSR_EP_NUM_MASK (0xF << 0)
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#define USB_DW_GRXSTSR_PKT_STS_MASK (0xF << 17)
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#define USB_DW_GRXSTSR_PKT_STS_OFFSET (17)
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#define USB_DW_GRXSTSR_PKT_CNT_MASK (0x7FF << 4)
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#define USB_DW_GRXSTSR_PKT_CNT_OFFSET (4)
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#define USB_DW_GRXSTSR_PKT_STS_OUT_DATA (2)
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#define USB_DW_GRXSTSR_PKT_STS_OUT_DATA_DONE (3)
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#define USB_DW_GRXSTSR_PKT_STS_SETUP_DONE (4)
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#define USB_DW_GRXSTSR_PKT_STS_SETUP (6)
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#define USB_DW_DTXFSTS_TXF_SPC_AVAIL_MASK (0xFFFF)
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#define USB_DW_CORE_RST_TIMEOUT_US 10000
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#define USB_DW_PLL_TIMEOUT_US 100
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#define USB_DW_EP_FIFO(ep) \
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(*(uint32_t *)(DT_INST_REG_ADDR(0) + 0x1000 * (ep + 1)))
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/* USB register block base address */
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#define USB_DW ((struct usb_dw_reg *)DT_INST_REG_ADDR(0))
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#define DW_USB_IN_EP_NUM (6)
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#define DW_USB_OUT_EP_NUM (4)
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#define DW_USB_MAX_PACKET_SIZE (64)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_ */
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