a1b77fd589
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
650 lines
17 KiB
C
650 lines
17 KiB
C
/*
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* Copyright (c) 2019 Brett Witherspoon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc13xx_cc26xx_uart
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#include <device.h>
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#include <errno.h>
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#include <sys/__assert.h>
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#include <power/power.h>
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#include <drivers/uart.h>
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#include <driverlib/ioc.h>
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#include <driverlib/prcm.h>
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#include <driverlib/uart.h>
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#include <ti/drivers/Power.h>
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#include <ti/drivers/power/PowerCC26X2.h>
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#define GET_PIN(n, pin_name) \
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DT_INST_PROP_BY_IDX(n, pin_name, 0)
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#define GET_PORT(n, pin_name) \
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DT_INST_PROP_BY_IDX(n, pin_name, 1)
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struct uart_cc13xx_cc26xx_data {
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struct uart_config uart_config;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t callback;
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void *user_data;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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Power_NotifyObj postNotify;
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bool tx_constrained;
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bool rx_constrained;
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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uint32_t pm_state;
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#endif
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};
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static inline struct uart_cc13xx_cc26xx_data *get_dev_data(struct device *dev)
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{
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return dev->driver_data;
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}
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static inline const struct uart_device_config *get_dev_conf(struct device *dev)
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{
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return dev->config_info;
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}
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static int uart_cc13xx_cc26xx_poll_in(struct device *dev, unsigned char *c)
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{
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if (!UARTCharsAvail(get_dev_conf(dev)->regs)) {
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return -1;
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}
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*c = UARTCharGetNonBlocking(get_dev_conf(dev)->regs);
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return 0;
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}
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static void uart_cc13xx_cc26xx_poll_out(struct device *dev, unsigned char c)
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{
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UARTCharPut(get_dev_conf(dev)->regs, c);
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/*
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* Need to wait for character to be transmitted to ensure cpu does not
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* enter standby when uart is busy
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*/
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while (UARTBusy(get_dev_conf(dev)->regs) == true) {
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}
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}
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static int uart_cc13xx_cc26xx_err_check(struct device *dev)
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{
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uint32_t flags = UARTRxErrorGet(get_dev_conf(dev)->regs);
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int error = (flags & UART_RXERROR_FRAMING ? UART_ERROR_FRAMING : 0) |
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(flags & UART_RXERROR_PARITY ? UART_ERROR_PARITY : 0) |
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(flags & UART_RXERROR_BREAK ? UART_BREAK : 0) |
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(flags & UART_RXERROR_OVERRUN ? UART_ERROR_OVERRUN : 0);
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UARTRxErrorClear(get_dev_conf(dev)->regs);
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return error;
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}
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static int uart_cc13xx_cc26xx_configure(struct device *dev,
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const struct uart_config *cfg)
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{
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uint32_t line_ctrl = 0;
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bool flow_ctrl;
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switch (cfg->parity) {
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case UART_CFG_PARITY_NONE:
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line_ctrl |= UART_CONFIG_PAR_NONE;
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break;
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case UART_CFG_PARITY_ODD:
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line_ctrl |= UART_CONFIG_PAR_ODD;
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break;
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case UART_CFG_PARITY_EVEN:
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line_ctrl |= UART_CONFIG_PAR_EVEN;
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break;
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case UART_CFG_PARITY_MARK:
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line_ctrl |= UART_CONFIG_PAR_ONE;
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break;
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case UART_CFG_PARITY_SPACE:
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line_ctrl |= UART_CONFIG_PAR_ZERO;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->stop_bits) {
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case UART_CFG_STOP_BITS_1:
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line_ctrl |= UART_CONFIG_STOP_ONE;
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break;
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case UART_CFG_STOP_BITS_2:
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line_ctrl |= UART_CONFIG_STOP_TWO;
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break;
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case UART_CFG_STOP_BITS_0_5:
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case UART_CFG_STOP_BITS_1_5:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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switch (cfg->data_bits) {
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case UART_CFG_DATA_BITS_5:
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line_ctrl |= UART_CONFIG_WLEN_5;
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break;
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case UART_CFG_DATA_BITS_6:
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line_ctrl |= UART_CONFIG_WLEN_6;
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break;
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case UART_CFG_DATA_BITS_7:
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line_ctrl |= UART_CONFIG_WLEN_7;
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break;
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case UART_CFG_DATA_BITS_8:
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line_ctrl |= UART_CONFIG_WLEN_8;
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break;
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default:
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return -EINVAL;
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}
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switch (cfg->flow_ctrl) {
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case UART_CFG_FLOW_CTRL_NONE:
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flow_ctrl = false;
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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flow_ctrl = true;
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break;
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case UART_CFG_FLOW_CTRL_DTR_DSR:
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return -ENOTSUP;
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default:
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return -EINVAL;
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}
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/* Disables UART before setting control registers */
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UARTConfigSetExpClk(get_dev_conf(dev)->regs,
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get_dev_conf(dev)->sys_clk_freq, cfg->baudrate,
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line_ctrl);
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/* Clear all UART interrupts */
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UARTIntClear(get_dev_conf(dev)->regs,
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UART_INT_OE | UART_INT_BE | UART_INT_PE |
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UART_INT_FE | UART_INT_RT | UART_INT_TX |
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UART_INT_RX | UART_INT_CTS);
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if (flow_ctrl) {
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UARTHwFlowControlEnable(get_dev_conf(dev)->regs);
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} else {
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UARTHwFlowControlDisable(get_dev_conf(dev)->regs);
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}
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/* Re-enable UART */
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UARTEnable(get_dev_conf(dev)->regs);
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/* Disabled FIFOs act as 1-byte-deep holding registers (character mode) */
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UARTFIFODisable(get_dev_conf(dev)->regs);
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get_dev_data(dev)->uart_config = *cfg;
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return 0;
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}
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static int uart_cc13xx_cc26xx_config_get(struct device *dev,
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struct uart_config *cfg)
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{
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*cfg = get_dev_data(dev)->uart_config;
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_cc13xx_cc26xx_fifo_fill(struct device *dev, const uint8_t *buf,
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int len)
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{
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int n = 0;
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while (n < len) {
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if (!UARTCharPutNonBlocking(get_dev_conf(dev)->regs, buf[n])) {
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break;
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}
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n++;
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}
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return n;
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}
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static int uart_cc13xx_cc26xx_fifo_read(struct device *dev, uint8_t *buf,
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const int len)
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{
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int c, n;
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n = 0;
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while (n < len) {
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c = UARTCharGetNonBlocking(get_dev_conf(dev)->regs);
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if (c == -1) {
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break;
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}
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buf[n++] = c;
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}
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return n;
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}
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static void uart_cc13xx_cc26xx_irq_tx_enable(struct device *dev)
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{
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#if defined(CONFIG_SYS_POWER_MANAGEMENT) && \
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defined(CONFIG_SYS_POWER_SLEEP_STATES)
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if (!get_dev_data(dev)->tx_constrained) {
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/*
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* When tx irq is enabled, it is implicit that we are expecting
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* to transmit using the uart, hence we should no longer go
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* into standby.
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*
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* Instead of using device_busy_set(), which currently does
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* not impact the PM policy, we specifically disable the
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* standby mode instead, since it is the power state that
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* would interfere with a transfer.
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*/
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sys_pm_ctrl_disable_state(SYS_POWER_STATE_SLEEP_2);
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get_dev_data(dev)->tx_constrained = true;
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}
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#endif
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UARTIntEnable(get_dev_conf(dev)->regs, UART_INT_TX);
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}
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static void uart_cc13xx_cc26xx_irq_tx_disable(struct device *dev)
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{
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UARTIntDisable(get_dev_conf(dev)->regs, UART_INT_TX);
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#if defined(CONFIG_SYS_POWER_MANAGEMENT) && \
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defined(CONFIG_SYS_POWER_SLEEP_STATES)
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if (get_dev_data(dev)->tx_constrained) {
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sys_pm_ctrl_enable_state(SYS_POWER_STATE_SLEEP_2);
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get_dev_data(dev)->tx_constrained = false;
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}
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#endif
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}
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static int uart_cc13xx_cc26xx_irq_tx_ready(struct device *dev)
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{
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return UARTSpaceAvail(get_dev_conf(dev)->regs) ? 1 : 0;
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}
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static void uart_cc13xx_cc26xx_irq_rx_enable(struct device *dev)
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{
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#if defined(CONFIG_SYS_POWER_MANAGEMENT) && \
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defined(CONFIG_SYS_POWER_SLEEP_STATES)
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/*
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* When rx is enabled, it is implicit that we are expecting
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* to receive from the uart, hence we can no longer go into
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* standby.
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*/
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if (!get_dev_data(dev)->rx_constrained) {
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sys_pm_ctrl_disable_state(SYS_POWER_STATE_SLEEP_2);
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get_dev_data(dev)->rx_constrained = true;
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}
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#endif
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UARTIntEnable(get_dev_conf(dev)->regs, UART_INT_RX);
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}
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static void uart_cc13xx_cc26xx_irq_rx_disable(struct device *dev)
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{
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#if defined(CONFIG_SYS_POWER_MANAGEMENT) && \
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defined(CONFIG_SYS_POWER_SLEEP_STATES)
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if (get_dev_data(dev)->rx_constrained) {
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sys_pm_ctrl_enable_state(SYS_POWER_STATE_SLEEP_2);
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get_dev_data(dev)->rx_constrained = false;
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}
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#endif
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UARTIntDisable(get_dev_conf(dev)->regs, UART_INT_RX);
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}
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static int uart_cc13xx_cc26xx_irq_tx_complete(struct device *dev)
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{
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return UARTBusy(get_dev_conf(dev)->regs) ? 0 : 1;
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}
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static int uart_cc13xx_cc26xx_irq_rx_ready(struct device *dev)
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{
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return UARTCharsAvail(get_dev_conf(dev)->regs) ? 1 : 0;
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}
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static void uart_cc13xx_cc26xx_irq_err_enable(struct device *dev)
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{
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return UARTIntEnable(get_dev_conf(dev)->regs,
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UART_INT_OE | UART_INT_BE | UART_INT_PE |
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UART_INT_FE);
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}
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static void uart_cc13xx_cc26xx_irq_err_disable(struct device *dev)
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{
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return UARTIntDisable(get_dev_conf(dev)->regs,
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UART_INT_OE | UART_INT_BE | UART_INT_PE |
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UART_INT_FE);
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}
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static int uart_cc13xx_cc26xx_irq_is_pending(struct device *dev)
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{
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uint32_t status = UARTIntStatus(get_dev_conf(dev)->regs, true);
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return status & (UART_INT_TX | UART_INT_RX) ? 1 : 0;
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}
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static int uart_cc13xx_cc26xx_irq_update(struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_cc13xx_cc26xx_irq_callback_set(
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struct device *dev, uart_irq_callback_user_data_t cb, void *user_data)
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{
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struct uart_cc13xx_cc26xx_data *data = get_dev_data(dev);
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data->callback = cb;
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data->user_data = user_data;
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}
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static void uart_cc13xx_cc26xx_isr(void *arg)
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{
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struct uart_cc13xx_cc26xx_data *data = get_dev_data(arg);
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if (data->callback) {
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data->callback(data->user_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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/*
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* ======== postNotifyFxn ========
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* Called by Power module when waking up the CPU from Standby, to support
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* the case when SYS_POWER_MANAGEMENT is set but DEVICE_POWER_MANAGEMENT is
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* not. The uart needs to be reconfigured afterwards unless Zephyr's device
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* PM turned it off, in which case it'd be responsible for turning it back
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* on and reconfiguring it.
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*/
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static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg,
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uintptr_t clientArg)
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{
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struct device *dev = (struct device *)clientArg;
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int ret = Power_NOTIFYDONE;
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int16_t res_id;
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/* Reconfigure the hardware if returning from standby */
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if (eventType == PowerCC26XX_AWAKE_STANDBY) {
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if (get_dev_conf(dev)->regs ==
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DT_INST_REG_ADDR(0)) {
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res_id = PowerCC26XX_PERIPH_UART0;
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} else { /* DT_INST_REG_ADDR(1) */
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res_id = PowerCC26X2_PERIPH_UART1;
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}
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if (Power_getDependencyCount(res_id) != 0) {
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/*
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* Reconfigure and enable UART only if not
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* actively powered down
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*/
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if (uart_cc13xx_cc26xx_configure(dev,
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&get_dev_data(dev)->uart_config) != 0) {
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ret = Power_NOTIFYERROR;
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}
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}
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}
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return (ret);
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}
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static int uart_cc13xx_cc26xx_set_power_state(struct device *dev,
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uint32_t new_state)
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{
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int ret = 0;
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if ((new_state == DEVICE_PM_ACTIVE_STATE) &&
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(new_state != get_dev_data(dev)->pm_state)) {
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if (get_dev_conf(dev)->regs ==
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DT_INST_REG_ADDR(0)) {
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Power_setDependency(PowerCC26XX_PERIPH_UART0);
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} else {
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Power_setDependency(PowerCC26X2_PERIPH_UART1);
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}
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/* Configure and enable UART */
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ret = uart_cc13xx_cc26xx_configure(dev,
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&get_dev_data(dev)->uart_config);
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if (ret == 0) {
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get_dev_data(dev)->pm_state = new_state;
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}
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} else {
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__ASSERT_NO_MSG(new_state == DEVICE_PM_LOW_POWER_STATE ||
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new_state == DEVICE_PM_SUSPEND_STATE ||
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new_state == DEVICE_PM_OFF_STATE);
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if (get_dev_data(dev)->pm_state == DEVICE_PM_ACTIVE_STATE) {
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UARTDisable(get_dev_conf(dev)->regs);
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/*
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* Release power dependency - i.e. potentially power
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* down serial domain.
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*/
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if (get_dev_conf(dev)->regs ==
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DT_INST_REG_ADDR(0)) {
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Power_releaseDependency(
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PowerCC26XX_PERIPH_UART0);
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} else {
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Power_releaseDependency(
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PowerCC26X2_PERIPH_UART1);
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}
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get_dev_data(dev)->pm_state = new_state;
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}
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}
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return ret;
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}
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static int uart_cc13xx_cc26xx_pm_control(struct device *dev, uint32_t ctrl_command,
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void *context, device_pm_cb cb, void *arg)
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{
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int ret = 0;
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if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
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uint32_t new_state = *((const uint32_t *)context);
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if (new_state != get_dev_data(dev)->pm_state) {
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ret = uart_cc13xx_cc26xx_set_power_state(dev,
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new_state);
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}
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} else {
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__ASSERT_NO_MSG(ctrl_command == DEVICE_PM_GET_POWER_STATE);
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*((uint32_t *)context) = get_dev_data(dev)->pm_state;
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}
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if (cb) {
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cb(dev, ret, context, arg);
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}
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return ret;
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}
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#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
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static const struct uart_driver_api uart_cc13xx_cc26xx_driver_api = {
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.poll_in = uart_cc13xx_cc26xx_poll_in,
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.poll_out = uart_cc13xx_cc26xx_poll_out,
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.err_check = uart_cc13xx_cc26xx_err_check,
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.configure = uart_cc13xx_cc26xx_configure,
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.config_get = uart_cc13xx_cc26xx_config_get,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_cc13xx_cc26xx_fifo_fill,
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.fifo_read = uart_cc13xx_cc26xx_fifo_read,
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.irq_tx_enable = uart_cc13xx_cc26xx_irq_tx_enable,
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.irq_tx_disable = uart_cc13xx_cc26xx_irq_tx_disable,
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.irq_tx_ready = uart_cc13xx_cc26xx_irq_tx_ready,
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.irq_rx_enable = uart_cc13xx_cc26xx_irq_rx_enable,
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.irq_rx_disable = uart_cc13xx_cc26xx_irq_rx_disable,
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.irq_tx_complete = uart_cc13xx_cc26xx_irq_tx_complete,
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.irq_rx_ready = uart_cc13xx_cc26xx_irq_rx_ready,
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.irq_err_enable = uart_cc13xx_cc26xx_irq_err_enable,
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.irq_err_disable = uart_cc13xx_cc26xx_irq_err_disable,
|
|
.irq_is_pending = uart_cc13xx_cc26xx_irq_is_pending,
|
|
.irq_update = uart_cc13xx_cc26xx_irq_update,
|
|
.irq_callback_set = uart_cc13xx_cc26xx_irq_callback_set,
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
};
|
|
|
|
#ifdef CONFIG_SYS_POWER_MANAGEMENT
|
|
#define UART_CC13XX_CC26XX_POWER_UART(n) \
|
|
do { \
|
|
get_dev_data(dev)->rx_constrained = false; \
|
|
get_dev_data(dev)->tx_constrained = false; \
|
|
\
|
|
/* Set Power dependencies */ \
|
|
if (DT_INST_REG_ADDR(n) == 0x40001000) { \
|
|
Power_setDependency(PowerCC26XX_PERIPH_UART0); \
|
|
} else { \
|
|
Power_setDependency(PowerCC26X2_PERIPH_UART1); \
|
|
} \
|
|
\
|
|
/* Register notification function */ \
|
|
Power_registerNotify(&get_dev_data(dev)->postNotify, \
|
|
PowerCC26XX_AWAKE_STANDBY, \
|
|
postNotifyFxn, (uintptr_t)dev); \
|
|
} while (0)
|
|
#else
|
|
#define UART_CC13XX_CC26XX_POWER_UART(n) \
|
|
do { \
|
|
uint32_t domain, periph; \
|
|
\
|
|
/* Enable UART power domain */ \
|
|
if (DT_INST_REG_ADDR(n) == 0x40001000) { \
|
|
domain = PRCM_DOMAIN_SERIAL; \
|
|
periph = PRCM_PERIPH_UART0; \
|
|
} else { \
|
|
domain = PRCM_DOMAIN_PERIPH; \
|
|
periph = PRCM_PERIPH_UART1; \
|
|
} \
|
|
PRCMPowerDomainOn(domain); \
|
|
\
|
|
/* Enable UART peripherals */ \
|
|
PRCMPeripheralRunEnable(periph); \
|
|
PRCMPeripheralSleepEnable(periph); \
|
|
\
|
|
/* Load PRCM settings */ \
|
|
PRCMLoadSet(); \
|
|
while (!PRCMLoadGet()) { \
|
|
continue; \
|
|
} \
|
|
\
|
|
/* UART should not be accessed until power domain is on. */ \
|
|
while (PRCMPowerDomainStatus(domain) != \
|
|
PRCM_DOMAIN_POWER_ON) { \
|
|
continue; \
|
|
} \
|
|
} while (0)
|
|
#endif
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#define UART_CC13XX_CC26XX_IRQ_CFG(n) \
|
|
do { \
|
|
UARTIntClear(get_dev_conf(dev)->regs, UART_INT_RX); \
|
|
\
|
|
IRQ_CONNECT(DT_INST_IRQN(n), \
|
|
DT_INST_IRQ(n, priority), \
|
|
uart_cc13xx_cc26xx_isr, \
|
|
DEVICE_GET(uart_cc13xx_cc26xx_##n), \
|
|
0); \
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
/* Causes an initial TX ready INT when TX INT enabled */\
|
|
UARTCharPutNonBlocking(get_dev_conf(dev)->regs, '\0'); \
|
|
} while (0)
|
|
|
|
#define UART_CC13XX_CC26XX_INT_FIELDS \
|
|
.callback = NULL, \
|
|
.user_data = NULL,
|
|
#else
|
|
#define UART_CC13XX_CC26XX_IRQ_CFG(n)
|
|
#define UART_CC13XX_CC26XX_INT_FIELDS
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
#define UART_CC13XX_CC26XX_DEVICE_DEFINE(n) \
|
|
DEVICE_DEFINE(uart_cc13xx_cc26xx_##n, DT_INST_LABEL(n), \
|
|
uart_cc13xx_cc26xx_init_##n, \
|
|
uart_cc13xx_cc26xx_pm_control, \
|
|
&uart_cc13xx_cc26xx_data_##n, &uart_cc13xx_cc26xx_config_##n,\
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&uart_cc13xx_cc26xx_driver_api)
|
|
|
|
#define UART_CC13XX_CC26XX_DEVICE_API_INIT(n) \
|
|
DEVICE_AND_API_INIT(uart_cc13xx_cc26xx_##n, DT_INST_LABEL(n), \
|
|
uart_cc13xx_cc26xx_init_##n, &uart_cc13xx_cc26xx_data_##n, \
|
|
&uart_cc13xx_cc26xx_config_##n, PRE_KERNEL_1, \
|
|
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&uart_cc13xx_cc26xx_driver_api)
|
|
|
|
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
#define UART_CC13XX_CC26XX_DEVICE_INIT(n) \
|
|
UART_CC13XX_CC26XX_DEVICE_DEFINE(n)
|
|
|
|
#define UART_CC13XX_CC26XX_INIT_PM_STATE \
|
|
do { \
|
|
get_dev_data(dev)->pm_state = DEVICE_PM_ACTIVE_STATE; \
|
|
} while (0)
|
|
#else
|
|
#define UART_CC13XX_CC26XX_DEVICE_INIT(n) \
|
|
UART_CC13XX_CC26XX_DEVICE_API_INIT(n)
|
|
|
|
#define UART_CC13XX_CC26XX_INIT_PM_STATE
|
|
#endif
|
|
|
|
#define UART_CC13XX_CC26XX_INIT_FUNC(n) \
|
|
static int uart_cc13xx_cc26xx_init_##n(struct device *dev) \
|
|
{ \
|
|
int ret; \
|
|
\
|
|
UART_CC13XX_CC26XX_INIT_PM_STATE; \
|
|
\
|
|
UART_CC13XX_CC26XX_POWER_UART(n); \
|
|
\
|
|
/* Configure IOC module to map UART signals to pins */ \
|
|
IOCPortConfigureSet(GET_PIN(n, tx_pin), GET_PORT(n, tx_pin),\
|
|
IOC_STD_OUTPUT); \
|
|
IOCPortConfigureSet(GET_PIN(n, rx_pin), GET_PORT(n, rx_pin),\
|
|
IOC_STD_INPUT); \
|
|
\
|
|
/* Configure and enable UART */ \
|
|
ret = uart_cc13xx_cc26xx_configure(dev, \
|
|
&get_dev_data(dev)->uart_config); \
|
|
\
|
|
/* Enable interrupts */ \
|
|
UART_CC13XX_CC26XX_IRQ_CFG(n); \
|
|
\
|
|
return ret; \
|
|
}
|
|
|
|
|
|
#define UART_CC13XX_CC26XX_INIT(n) \
|
|
DEVICE_DECLARE(uart_cc13xx_cc26xx_##n); \
|
|
\
|
|
UART_CC13XX_CC26XX_INIT_FUNC(n); \
|
|
\
|
|
static const struct uart_device_config \
|
|
uart_cc13xx_cc26xx_config_##n = { \
|
|
.regs = DT_INST_REG_ADDR(n), \
|
|
.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, \
|
|
clock_frequency) \
|
|
}; \
|
|
\
|
|
static struct uart_cc13xx_cc26xx_data \
|
|
uart_cc13xx_cc26xx_data_##n = { \
|
|
.uart_config = { \
|
|
.baudrate = DT_INST_PROP(n, current_speed), \
|
|
.parity = UART_CFG_PARITY_NONE, \
|
|
.stop_bits = UART_CFG_STOP_BITS_1, \
|
|
.data_bits = UART_CFG_DATA_BITS_8, \
|
|
.flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
|
|
}, \
|
|
UART_CC13XX_CC26XX_INT_FIELDS \
|
|
}; \
|
|
\
|
|
UART_CC13XX_CC26XX_DEVICE_INIT(n);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_CC13XX_CC26XX_INIT)
|