a1b77fd589
git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
273 lines
6.5 KiB
C
273 lines
6.5 KiB
C
/*
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* Copyright (c) 2017 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nordic_nrf_sw_pwm
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#include <soc.h>
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#include <drivers/pwm.h>
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#include <nrf_peripherals.h>
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#define LOG_LEVEL CONFIG_PWM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_nrf5_sw);
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/* One compare channel is needed to set the PWM period, hence +1. */
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#if ((DT_INST_PROP(0, channel_count) + 1) > \
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(_CONCAT( \
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_CONCAT(TIMER, DT_INST_PROP(0, timer_instance)), \
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_CC_NUM)))
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#error "Invalid number of PWM channels configured."
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#endif
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#define PWM_0_MAP_SIZE DT_INST_PROP(0, channel_count)
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struct pwm_config {
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NRF_TIMER_Type *timer;
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uint8_t gpiote_base;
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uint8_t ppi_base;
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uint8_t map_size;
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uint8_t prescaler;
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};
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struct chan_map {
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uint32_t pwm;
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uint32_t pulse_cycles;
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};
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struct pwm_data {
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uint32_t period_cycles;
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struct chan_map map[PWM_0_MAP_SIZE];
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};
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static uint32_t pwm_period_check(struct pwm_data *data, uint8_t map_size,
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uint32_t pwm, uint32_t period_cycles,
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uint32_t pulse_cycles)
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{
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uint8_t i;
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/* allow 0% and 100% duty cycle, as it does not use PWM. */
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if ((pulse_cycles == 0U) || (pulse_cycles == period_cycles)) {
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return 0;
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}
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/* fail if requested period does not match already running period */
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for (i = 0U; i < map_size; i++) {
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if ((data->map[i].pwm != pwm) &&
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(data->map[i].pulse_cycles != 0U) &&
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(period_cycles != data->period_cycles)) {
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return -EINVAL;
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}
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}
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return 0;
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}
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static uint8_t pwm_channel_map(struct pwm_data *data, uint8_t map_size,
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uint32_t pwm)
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{
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uint8_t i;
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/* find pin, if already present */
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for (i = 0U; i < map_size; i++) {
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if (pwm == data->map[i].pwm) {
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return i;
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}
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}
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/* find a free entry */
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i = map_size;
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while (i--) {
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if (data->map[i].pulse_cycles == 0U) {
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break;
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}
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}
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return i;
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}
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static int pwm_nrf5_sw_pin_set(struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_config *config;
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NRF_TIMER_Type *timer;
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struct pwm_data *data;
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uint8_t ppi_index;
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uint8_t channel;
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uint16_t div;
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uint32_t ret;
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config = (const struct pwm_config *)dev->config_info;
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timer = config->timer;
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data = dev->driver_data;
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if (flags) {
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/* PWM polarity not supported (yet?) */
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return -ENOTSUP;
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}
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/* check if requested period is allowed while other channels are
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* active.
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*/
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ret = pwm_period_check(data, config->map_size, pwm, period_cycles,
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pulse_cycles);
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if (ret) {
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LOG_ERR("Incompatible period");
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return ret;
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}
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/* map pwm pin to GPIOTE config/channel */
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channel = pwm_channel_map(data, config->map_size, pwm);
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if (channel >= config->map_size) {
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LOG_ERR("No more channels available");
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return -ENOMEM;
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}
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LOG_DBG("PWM %d, period %u, pulse %u", pwm,
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period_cycles, pulse_cycles);
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/* clear GPIOTE config */
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NRF_GPIOTE->CONFIG[config->gpiote_base + channel] = 0;
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/* clear PPI used */
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ppi_index = config->ppi_base + (channel << 1);
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NRF_PPI->CHENCLR = BIT(ppi_index) | BIT(ppi_index + 1);
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/* configure GPIO pin as output */
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NRF_GPIO->DIRSET = BIT(pwm);
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if (pulse_cycles == 0U) {
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/* 0% duty cycle, keep pin low */
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NRF_GPIO->OUTCLR = BIT(pwm);
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goto pin_set_pwm_off;
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} else if (pulse_cycles == period_cycles) {
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/* 100% duty cycle, keep pin high */
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NRF_GPIO->OUTSET = BIT(pwm);
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goto pin_set_pwm_off;
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} else {
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/* x% duty cycle, start PWM with pin low */
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NRF_GPIO->OUTCLR = BIT(pwm);
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}
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/* TODO: if the assigned NRF_TIMER supports higher bit resolution,
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* use that info in config struct and setup accordingly.
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*/
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/* calc div, to scale down to fit in 16 bits */
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div = period_cycles >> 16;
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timer->EVENTS_COMPARE[channel] = 0;
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timer->EVENTS_COMPARE[config->map_size] = 0;
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timer->CC[channel] = pulse_cycles >> div;
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timer->CC[config->map_size] = period_cycles >> div;
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timer->TASKS_CLEAR = 1;
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/* configure GPIOTE, toggle with initialise output high */
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NRF_GPIOTE->CONFIG[config->gpiote_base + channel] = 0x00130003 |
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(pwm << 8);
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/* setup PPI */
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NRF_PPI->CH[ppi_index].EEP = (uint32_t)
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&(timer->EVENTS_COMPARE[channel]);
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NRF_PPI->CH[ppi_index].TEP = (uint32_t)
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&(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CH[ppi_index + 1].EEP = (uint32_t)
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&(timer->EVENTS_COMPARE[
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config->map_size]);
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NRF_PPI->CH[ppi_index + 1].TEP = (uint32_t)
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&(NRF_GPIOTE->TASKS_OUT[channel]);
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NRF_PPI->CHENSET = BIT(ppi_index) | BIT(ppi_index + 1);
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/* start timer, hence PWM */
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timer->TASKS_START = 1;
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/* store the pwm/pin and its param */
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data->period_cycles = period_cycles;
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data->map[channel].pwm = pwm;
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data->map[channel].pulse_cycles = pulse_cycles;
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return 0;
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pin_set_pwm_off:
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data->map[channel].pulse_cycles = 0U;
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bool pwm_active = false;
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/* stop timer if all channels are inactive */
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for (channel = 0U; channel < config->map_size; channel++) {
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if (data->map[channel].pulse_cycles) {
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pwm_active = true;
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break;
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}
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}
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if (!pwm_active) {
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/* No active PWM, stop timer */
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timer->TASKS_STOP = 1;
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}
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return 0;
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}
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static int pwm_nrf5_sw_get_cycles_per_sec(struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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const struct pwm_config *config;
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config = (const struct pwm_config *)dev->config_info;
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/* HF timer frequency is derived from 16MHz source with a prescaler */
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*cycles = 16000000UL / BIT(config->prescaler);
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return 0;
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}
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static const struct pwm_driver_api pwm_nrf5_sw_drv_api_funcs = {
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.pin_set = pwm_nrf5_sw_pin_set,
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.get_cycles_per_sec = pwm_nrf5_sw_get_cycles_per_sec,
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};
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static int pwm_nrf5_sw_init(struct device *dev)
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{
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const struct pwm_config *config;
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NRF_TIMER_Type *timer;
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config = (const struct pwm_config *)dev->config_info;
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timer = config->timer;
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/* setup HF timer */
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timer->MODE = TIMER_MODE_MODE_Timer;
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timer->PRESCALER = config->prescaler;
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timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit;
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/* TODO: set shorts according to map_size if not 3, i.e. if NRF_TIMER
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* supports more than 4 compares, then more channels can be supported.
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*/
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timer->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk;
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return 0;
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}
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static const struct pwm_config pwm_nrf5_sw_0_config = {
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.timer = _CONCAT(NRF_TIMER, DT_INST_PROP(0, timer_instance)),
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.ppi_base = DT_INST_PROP(0, ppi_base),
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.gpiote_base = DT_INST_PROP(0, gpiote_base),
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.map_size = PWM_0_MAP_SIZE,
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.prescaler = DT_INST_PROP(0, clock_prescaler),
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};
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static struct pwm_data pwm_nrf5_sw_0_data;
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DEVICE_AND_API_INIT(pwm_nrf5_sw_0,
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DT_INST_LABEL(0),
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pwm_nrf5_sw_init,
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&pwm_nrf5_sw_0_data,
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&pwm_nrf5_sw_0_config,
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POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&pwm_nrf5_sw_drv_api_funcs);
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