08ed93fed9
With this refactoring of pcie directory, RC drivers are placed under host/ directory, EP drivers are placed under endpoint/ directory and they are completely independent of each other. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
87 lines
1.5 KiB
C
87 lines
1.5 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <stdbool.h>
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#include <drivers/pcie/pcie.h>
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#if CONFIG_PCIE_MSI
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#include <drivers/pcie/msi.h>
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#endif
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/* functions documented in drivers/pcie/pcie.h */
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bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id)
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{
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uint32_t data;
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data = pcie_conf_read(bdf, PCIE_CONF_ID);
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if (data == PCIE_ID_NONE) {
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return false;
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}
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if (id == PCIE_ID_NONE) {
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return true;
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}
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return (id == data);
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}
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void pcie_set_cmd(pcie_bdf_t bdf, uint32_t bits, bool on)
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{
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uint32_t cmdstat;
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cmdstat = pcie_conf_read(bdf, PCIE_CONF_CMDSTAT);
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if (on) {
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cmdstat |= bits;
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} else {
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cmdstat &= ~bits;
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}
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pcie_conf_write(bdf, PCIE_CONF_CMDSTAT, cmdstat);
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}
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uintptr_t pcie_get_mbar(pcie_bdf_t bdf, unsigned int index)
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{
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uint32_t reg, bar;
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uintptr_t addr = PCIE_CONF_BAR_NONE;
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reg = PCIE_CONF_BAR0;
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for (bar = 0; bar < index && reg <= PCIE_CONF_BAR5; bar++) {
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if (PCIE_CONF_BAR_64(pcie_conf_read(bdf, reg++))) {
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reg++;
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}
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}
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if (bar == index) {
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addr = pcie_conf_read(bdf, reg++);
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if (IS_ENABLED(CONFIG_64BIT) && PCIE_CONF_BAR_64(addr)) {
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addr |= ((uint64_t)pcie_conf_read(bdf, reg)) << 32;
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}
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}
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return PCIE_CONF_BAR_ADDR(addr);
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}
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unsigned int pcie_wired_irq(pcie_bdf_t bdf)
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{
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uint32_t data = pcie_conf_read(bdf, PCIE_CONF_INTR);
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return PCIE_CONF_INTR_IRQ(data);
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}
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void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq)
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{
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#if CONFIG_PCIE_MSI
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if (pcie_set_msi(bdf, irq)) {
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return;
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}
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#endif
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irq_enable(irq);
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}
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