b4a7eed82e
The dw_ictl interrupt controller is an interrupt aggregator supporting multi-level interrupts. Therefore, it needs to be initialized earlier than any downstream interrupt controllers and devices. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
# Copyright (c) 2019 Intel Corporation
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
menuconfig DW_ICTL
|
|
bool "Designware Interrupt Controller"
|
|
depends on MULTI_LEVEL_INTERRUPTS
|
|
help
|
|
Designware Interrupt Controller can be used as a 2nd level interrupt
|
|
controller which combines several sources of interrupt into one line
|
|
that is then routed to the 1st level interrupt controller.
|
|
|
|
if DW_ICTL
|
|
|
|
config DW_ICTL_NAME
|
|
string "Name for Designware Interrupt Controller"
|
|
default "DW_ICTL"
|
|
help
|
|
Give a name for the instance of Designware Interrupt Controller
|
|
|
|
config DW_ICTL_OFFSET
|
|
int "Parent interrupt number to which DW_ICTL maps"
|
|
default 0
|
|
help
|
|
Parent interrupt number to which DW_ICTL maps
|
|
|
|
config DW_ISR_TBL_OFFSET
|
|
int "Offset in the SW ISR Table"
|
|
default 0
|
|
help
|
|
This indicates the offset in the SW_ISR_TABLE beginning from where
|
|
the ISRs for Designware Interrupt Controller are assigned.
|
|
|
|
config DW_ICTL_INIT_PRIORITY
|
|
int "Init priority for DW interrupt controller"
|
|
default 48
|
|
help
|
|
DesignWare Interrupt Controller initialization priority.
|
|
|
|
endif # DW_ICTL
|