9e627ed6d2
Fairly straightforward example of how to deal with PCIe. The code considers whether a particular instance is PCIe or not on a per-instance basis, so DEVICE_MMIO_ROM is not conditionally defined. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/* dw_i2c.h - header for Design Ware I2C operations */
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_H_
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#define ZEPHYR_DRIVERS_I2C_I2C_DW_H_
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#include <drivers/i2c.h>
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#include <stdbool.h>
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#define DT_DRV_COMPAT snps_designware_i2c
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#if DT_INST_PROP(0, pcie) || \
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DT_INST_PROP(1, pcie) || \
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DT_INST_PROP(2, pcie) || \
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DT_INST_PROP(3, pcie) || \
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DT_INST_PROP(4, pcie) || \
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DT_INST_PROP(5, pcie) || \
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DT_INST_PROP(6, pcie) || \
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DT_INST_PROP(7, pcie)
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BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE");
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#define I2C_DW_PCIE_ENABLED
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#include <drivers/pcie/pcie.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2C_DW_MAGIC_KEY 0x44570140
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typedef void (*i2c_isr_cb_t)(struct device *port);
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#define IC_ACTIVITY (1 << 0)
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#define IC_ENABLE_BIT (1 << 0)
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/* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */
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#define I2C_DW_STATE_READY (0)
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#define I2C_DW_CMD_SEND (1 << 0)
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#define I2C_DW_CMD_RECV (1 << 1)
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#define I2C_DW_CMD_ERROR (1 << 2)
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#define I2C_DW_BUSY (1 << 3)
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#define DW_ENABLE_TX_INT_I2C_MASTER (DW_INTR_STAT_TX_OVER | \
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DW_INTR_STAT_TX_EMPTY | \
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DW_INTR_STAT_TX_ABRT | \
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DW_INTR_STAT_STOP_DET)
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#define DW_ENABLE_RX_INT_I2C_MASTER (DW_INTR_STAT_RX_UNDER | \
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DW_INTR_STAT_RX_OVER | \
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DW_INTR_STAT_RX_FULL | \
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DW_INTR_STAT_STOP_DET)
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#define DW_ENABLE_TX_INT_I2C_SLAVE (DW_INTR_STAT_RD_REQ | \
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DW_INTR_STAT_TX_ABRT | \
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DW_INTR_STAT_STOP_DET)
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#define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | \
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DW_INTR_STAT_STOP_DET)
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#define DW_DISABLE_ALL_I2C_INT 0x00000000
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/* IC_CON Low count and high count default values */
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/* TODO verify values for high and fast speed */
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#define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4)
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#define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5)
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#define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8)
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#define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8)
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#define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8)
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#define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8)
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/*
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* DesignWare speed values don't directly translate from the Zephyr speed
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* selections in include/i2c.h so here we do a little translation
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*/
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#define I2C_DW_SPEED_STANDARD 0x1
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#define I2C_DW_SPEED_FAST 0x2
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#define I2C_DW_SPEED_FAST_PLUS 0x2
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#define I2C_DW_SPEED_HIGH 0x3
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/*
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* These values have been randomly selected. It would be good to test different
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* watermark levels for performance capabilities
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*/
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#define I2C_DW_TX_WATERMARK 2
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#define I2C_DW_RX_WATERMARK 7
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#define I2C_DW_FIFO_DEPTH 16
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struct i2c_dw_rom_config {
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DEVICE_MMIO_ROM;
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i2c_isr_cb_t config_func;
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uint32_t bitrate;
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#ifdef I2C_DW_PCIE_ENABLED
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bool pcie;
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pcie_bdf_t pcie_bdf;
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pcie_id_t pcie_id;
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#endif /* I2C_DW_PCIE_ENABLED */
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};
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struct i2c_dw_dev_config {
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DEVICE_MMIO_RAM;
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struct k_sem device_sync_sem;
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uint32_t app_config;
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uint8_t *xfr_buf;
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uint32_t xfr_len;
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uint32_t rx_pending;
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uint16_t hcnt;
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uint16_t lcnt;
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volatile uint8_t state; /* last direction of transfer */
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uint8_t request_bytes;
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uint8_t xfr_flags;
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bool support_hs_mode;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_H_ */
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