69f0e3b15f
Add support for STM32L0X using the generic STM32 backend. This is quite a significant change since the L0 series uses a slightly different flash controller. Refactor the generic backend to better support different block sizes and the L0's register interface. Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
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#define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#endif
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struct flash_stm32_priv {
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FLASH_TypeDef *regs;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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#endif
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struct k_sem sem;
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};
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#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#define FLASH_STM32_WRITE_BLOCK_SIZE \
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DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
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#else
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#error Flash write block size not available
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/* Flash Write block size is extracted from device tree */
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/* as flash node property 'write-block-size' */
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#endif
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#define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->driver_data))
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#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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static inline bool flash_stm32_range_exists(struct device *dev,
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off_t offset,
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uint32_t len)
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{
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struct flash_pages_info info;
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return !(flash_get_page_info_by_offs(dev, offset, &info) ||
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flash_get_page_info_by_offs(dev, offset + len - 1, &info));
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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bool flash_stm32_valid_range(struct device *dev, off_t offset,
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uint32_t len, bool write);
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int flash_stm32_write_range(struct device *dev, unsigned int offset,
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const void *data, unsigned int len);
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int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
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unsigned int len);
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int flash_stm32_wait_flash_idle(struct device *dev);
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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int flash_stm32_check_status(struct device *dev);
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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void flash_stm32_page_layout(struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size);
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#endif
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#endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
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