5c0687e58b
This patch activates the boost mode for the main regulator when the system frequency above 150MHz for stm32g4xx soc series. To save power, the boost mode should be disabled below 150MHz. Signed-off-by: Francois Ramu <francois.ramu@st.com>
74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/* Macros to fill up division factors values */
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#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) z_pllm(v)
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#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
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pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
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pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
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/* set power boost mode for sys clock greater than 150MHz */
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if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
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LL_PWR_EnableRange1BoostMode();
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}
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#ifdef CONFIG_CLOCK_STM32_LSE
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/* LSE belongs to the back-up domain, enable access.*/
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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/* Enable LSE Oscillator (32.768 kHz) */
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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/* Wait for LSE ready */
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}
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LL_PWR_DisableBkUpAccess();
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#endif
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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