4acac3e9ef
- Support PLL for Higher Frequencies 80,160,240 MHz - Support XTAL Frequencies 26MHz, 40MHz - Clock Driver can't be disabled, because all of the other drivers will depend on it to get their operating Frequency based on chosen clock source (XTAL/PLL). - Add needed references to BBPLL i2c bus ROM functions. - Add `rtc` node to Device Tree. - Since All Peripherals Frequency is depending on CPU_CLK Source, `clock-source` property added to CPU node Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
322 lines
8.8 KiB
C
322 lines
8.8 KiB
C
/*
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* Copyright (c) 2020 Mohamed ElShahawi.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#include <dt-bindings/clock/esp32_clock.h>
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#include <soc/dport_reg.h>
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#include <soc/rtc.h>
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#include <soc/rtc_cntl_reg.h>
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#include <drivers/uart.h>
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#include <soc/apb_ctrl_reg.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include "clock_control_esp32.h"
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struct esp32_clock_config {
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uint32_t clk_src_sel;
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uint32_t cpu_freq;
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uint32_t xtal_freq_sel;
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uint32_t xtal_div;
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};
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struct control_regs {
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/** Peripheral control register */
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uint32_t clk;
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/** Peripheral reset register */
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uint32_t rst;
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};
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struct bbpll_cfg {
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uint8_t div_ref;
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uint8_t div7_0;
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uint8_t div10_8;
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uint8_t lref;
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uint8_t dcur;
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uint8_t bw;
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};
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struct pll_cfg {
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uint8_t dbias_wak;
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uint8_t endiv5;
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uint8_t bbadc_dsmp;
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struct bbpll_cfg bbpll[2];
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};
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#define PLL_APB_CLK_FREQ 80
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#define RTC_PLL_FREQ_320M 0
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#define RTC_PLL_FREQ_480M 1
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#define DPORT_CPUPERIOD_SEL_80 0
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#define DPORT_CPUPERIOD_SEL_160 1
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#define DPORT_CPUPERIOD_SEL_240 2
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#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config_info))
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#define GET_REG_BANK(module_id) ((uint32_t)module_id / 32U)
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#define GET_REG_OFFSET(module_id) ((uint32_t)module_id % 32U)
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#define CLOCK_REGS_BANK_COUNT 3
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const struct control_regs clock_control_regs[CLOCK_REGS_BANK_COUNT] = {
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[0] = { .clk = DPORT_PERIP_CLK_EN_REG, .rst = DPORT_PERIP_RST_EN_REG },
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[1] = { .clk = DPORT_PERI_CLK_EN_REG, .rst = DPORT_PERI_RST_EN_REG },
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[2] = { .clk = DPORT_WIFI_CLK_EN_REG, .rst = DPORT_CORE_RST_EN_REG }
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};
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static uint32_t const xtal_freq[] = {
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[ESP32_CLK_XTAL_40M] = 40,
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[ESP32_CLK_XTAL_26M] = 26
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};
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const struct pll_cfg pll_config[] = {
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[RTC_PLL_FREQ_320M] = {
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.dbias_wak = 0,
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.endiv5 = BBPLL_ENDIV5_VAL_320M,
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.bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_320M,
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.bbpll[ESP32_CLK_XTAL_40M] = {
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/* 40mhz */
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.div_ref = 0,
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.div7_0 = 32,
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.div10_8 = 0,
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.lref = 0,
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.dcur = 6,
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.bw = 3,
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},
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.bbpll[ESP32_CLK_XTAL_26M] = {
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/* 26mhz */
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.div_ref = 12,
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.div7_0 = 224,
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.div10_8 = 4,
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.lref = 1,
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.dcur = 0,
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.bw = 1,
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}
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},
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[RTC_PLL_FREQ_480M] = {
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.dbias_wak = 0,
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.endiv5 = BBPLL_ENDIV5_VAL_480M,
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.bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_480M,
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.bbpll[ESP32_CLK_XTAL_40M] = {
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/* 40mhz */
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.div_ref = 0,
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.div7_0 = 28,
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.div10_8 = 0,
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.lref = 0,
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.dcur = 6,
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.bw = 3,
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},
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.bbpll[ESP32_CLK_XTAL_26M] = {
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/* 26mhz */
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.div_ref = 12,
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.div7_0 = 144,
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.div10_8 = 4,
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.lref = 1,
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.dcur = 0,
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.bw = 1,
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}
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}
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};
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static void bbpll_configure(rtc_xtal_freq_t xtal_freq, uint32_t pll_freq)
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{
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uint8_t dbias_wak = 0;
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const struct pll_cfg *cfg = &pll_config[pll_freq];
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const struct bbpll_cfg *bb_cfg = &pll_config[pll_freq].bbpll[xtal_freq];
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/* Enable PLL, Clear PowerDown (_PD) flags */
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BIAS_I2C_FORCE_PD |
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RTC_CNTL_BB_I2C_FORCE_PD |
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RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* reset BBPLL configuration */
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
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/* voltage needs to be changed for CPU@240MHz or
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* 80MHz Flash (because of internal flash regulator)
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*/
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if (pll_freq == RTC_PLL_FREQ_320M) {
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dbias_wak = DIG_DBIAS_80M_160M;
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} else { /* RTC_PLL_FREQ_480M */
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dbias_wak = DIG_DBIAS_240M;
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}
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/* Configure the voltage */
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias_wak);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, cfg->endiv5);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, cfg->bbadc_dsmp);
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uint8_t i2c_bbpll_lref = (bb_cfg->lref << 7) | (bb_cfg->div10_8 << 4) | (bb_cfg->div_ref);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, bb_cfg->div7_0);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, ((bb_cfg->bw << 6) | bb_cfg->dcur));
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}
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static void cpuclk_pll_configure(uint32_t xtal_freq, uint32_t cpu_freq)
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{
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uint32_t pll_freq = RTC_PLL_FREQ_320M;
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uint32_t cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
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switch (cpu_freq) {
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case ESP32_CLK_CPU_80M:
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pll_freq = RTC_PLL_FREQ_320M;
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cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
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break;
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case ESP32_CLK_CPU_160M:
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pll_freq = RTC_PLL_FREQ_320M;
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cpu_period_sel = DPORT_CPUPERIOD_SEL_160;
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break;
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case ESP32_CLK_CPU_240M:
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pll_freq = RTC_PLL_FREQ_480M;
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cpu_period_sel = DPORT_CPUPERIOD_SEL_240;
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break;
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}
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/* Configure PLL based on XTAL Value */
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bbpll_configure(xtal_freq, pll_freq);
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/* Set CPU Speed (80,160,240) */
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, cpu_period_sel);
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/* Set PLL as CPU Clock Source */
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
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/*
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* Update REF_Tick,
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* if PLL is the cpu clock source, APB frequency is always 80MHz
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*/
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REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, PLL_APB_CLK_FREQ - 1);
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}
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static int clock_control_esp32_on(struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t bank = GET_REG_BANK(sys);
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uint32_t offset = GET_REG_OFFSET(sys);
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__ASSERT_NO_MSG(bank >= CLOCK_REGS_BANK_COUNT);
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esp32_set_mask32(BIT(offset), clock_control_regs[bank].clk);
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esp32_clear_mask32(BIT(offset), clock_control_regs[bank].rst);
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return 0;
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}
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static int clock_control_esp32_off(struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t bank = GET_REG_BANK(sys);
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uint32_t offset = GET_REG_OFFSET(sys);
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__ASSERT_NO_MSG(bank >= CLOCK_REGS_BANK_COUNT);
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esp32_clear_mask32(BIT(offset), clock_control_regs[bank].clk);
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esp32_set_mask32(BIT(offset), clock_control_regs[bank].rst);
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return 0;
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}
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static enum clock_control_status clock_control_esp32_get_status(struct device *dev,
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clock_control_subsys_t sys)
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{
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ARG_UNUSED(dev);
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uint32_t bank = GET_REG_BANK(sys);
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uint32_t offset = GET_REG_OFFSET(sys);
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if (DPORT_GET_PERI_REG_MASK(clock_control_regs[bank].clk, BIT(offset))) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static int clock_control_esp32_get_rate(struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(sub_system);
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uint32_t xtal_freq_sel = DEV_CFG(dev)->xtal_freq_sel;
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uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
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switch (soc_clk_sel) {
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case RTC_CNTL_SOC_CLK_SEL_XTL:
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*rate = xtal_freq[xtal_freq_sel];
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return 0;
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case RTC_CNTL_SOC_CLK_SEL_PLL:
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*rate = MHZ(80);
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return 0;
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default:
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*rate = 0;
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return -ENOTSUP;
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}
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}
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static int clock_control_esp32_init(struct device *dev)
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{
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struct esp32_clock_config *cfg = DEV_CFG(dev);
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/* Wait for UART first before changing freq to avoid garbage on console */
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esp32_rom_uart_tx_wait_idle(0);
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switch (cfg->clk_src_sel) {
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case ESP32_CLK_SRC_XTAL:
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, cfg->xtal_div);
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/* adjust ref_tick */
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REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq[cfg->xtal_freq_sel] - 1);
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/* switch clock source */
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
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break;
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case ESP32_CLK_SRC_PLL:
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cpuclk_pll_configure(cfg->xtal_freq_sel, cfg->cpu_freq);
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break;
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default:
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return -EINVAL;
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}
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/* Re-calculate the CCOUNT register value to make time calculation correct.
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* This should be updated on each frequency change
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* New CCOUNT = Current CCOUNT * (new freq / old freq)
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*/
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XTHAL_SET_CCOUNT((uint64_t)XTHAL_GET_CCOUNT() * cfg->cpu_freq / xtal_freq[cfg->xtal_freq_sel]);
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return 0;
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}
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static const struct clock_control_driver_api clock_control_esp32_api = {
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.on = clock_control_esp32_on,
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.off = clock_control_esp32_off,
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.get_rate = clock_control_esp32_get_rate,
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.get_status = clock_control_esp32_get_status,
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};
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static const struct esp32_clock_config esp32_clock_config0 = {
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.clk_src_sel = DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_source),
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.cpu_freq = DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_frequency),
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.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
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.xtal_div = DT_INST_PROP(0, xtal_div),
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};
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DEVICE_AND_API_INIT(clk_esp32, DT_INST_LABEL(0),
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&clock_control_esp32_init,
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NULL, &esp32_clock_config0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
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&clock_control_esp32_api);
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == MHZ(DT_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_frequency)),
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
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BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cadence_tensilica_xtensa_lx6), clock_source),
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"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
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