907c545837
Allow CLOCK_STM32_PLL_PREDIV1 option for STM32F3 series; correct and extend option descriptions. Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
# STM32F0 and STM32F3 PLL configuration options
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# Copyright (c) 2019 Linaro
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
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config CLOCK_STM32_PLL_PREDIV
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int "PREDIV Prescaler"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 16
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help
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PREDIV is a PLL clock signal prescaler for the HSE output.
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It is supported by those parts that do not support PREDIV1.
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If configured on a non-supported part, this config will be ignored.
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Allowed values: 1 - 16.
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 16
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help
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PREDIV1 is a PLL clock signal prescaler for any PLL input.
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It is supported by STM32F04xx, STM32F07xx, STM32F09xx, STM32F030xC,
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STM32F302xE, STM32F303xE and STM32F39xx parts.
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If configured on a non-supported part, this config will be ignored.
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Allowed values: 1 - 16.
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 6
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range 2 16
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help
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PLL multiplier, allowed values: 2-16.
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PLL output must not exceed 48MHz for STM32F0 series
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or 72MHz for STM32F3 series.
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endif # SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
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