zephyr/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig
Andrew Boie a9670ab5cf boards: centralize QEMU icount management
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-24 20:28:36 -04:00

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# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_RISCV_SIFIVE_FREEDOM=y
CONFIG_SOC_RISCV_SIFIVE_FREEDOM=y
CONFIG_BOARD_QEMU_RISCV64=y
CONFIG_CONSOLE=y
CONFIG_PRINTK=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_PLIC=y
CONFIG_PINMUX=y
CONFIG_PINMUX_SIFIVE=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_GPIO=y
CONFIG_GPIO_SIFIVE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
CONFIG_STACK_SENTINEL=y
CONFIG_TEST_EXTRA_STACKSIZE=256
CONFIG_QEMU_ICOUNT_SHIFT=6