d72d903581
As a slow FPGA platform with max. freq < 25 Mhz, the default CON_SYS_CLOCK_TICKS_PER_SEC=10000 is not suitable. CON_SYS_CLOCK_TICKS_PER_SEC=100 is a better value. Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
21 lines
453 B
Plaintext
21 lines
453 B
Plaintext
# SPDX-License-Identifier: Apache-2.0
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CONFIG_CPU_ARCEM=y
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CONFIG_SOC_EMSK=y
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CONFIG_SOC_EMSK_EM7D=y
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CONFIG_BOARD_EM_STARTERKIT=y
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CONFIG_BOARD_EM_STARTERKIT_R22=y
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CONFIG_XIP=n
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
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CONFIG_BUILD_NO_GAP_FILL=y
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_PRINTK=y
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CONFIG_ARCV2_INTERRUPT_UNIT=y
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CONFIG_ARCV2_TIMER=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_GPIO=y
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CONFIG_ARC_MPU_ENABLE=y
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