b61f448a3f
This adds the necessary bits to build the Xtensa HAL as a module, and removes the bits to use the HAL built with the Zephyr SDK. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
134 lines
2.7 KiB
C
134 lines
2.7 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <kernel_structs.h>
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#include <inttypes.h>
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#include <kernel_arch_data.h>
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#include <xtensa/config/specreg.h>
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#include <xtensa-asm2-context.h>
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#include <logging/log.h>
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LOG_MODULE_DECLARE(os);
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#ifdef XT_SIMULATOR
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#include <xtensa/simcall.h>
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#endif
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/* Need to do this as a macro since regnum must be an immediate value */
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#define get_sreg(regnum_p) ({ \
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unsigned int retval; \
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__asm__ volatile( \
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"rsr %[retval], %[regnum]\n\t" \
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: [retval] "=r" (retval) \
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: [regnum] "i" (regnum_p)); \
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retval; \
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})
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char *z_xtensa_exccause(unsigned int cause_code)
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{
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#if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
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switch (cause_code) {
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case 0:
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return "illegal instruction";
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case 1:
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return "syscall";
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case 2:
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return "instr fetch error";
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case 3:
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return "load/store error";
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case 4:
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return "level-1 interrupt";
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case 5:
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return "alloca";
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case 6:
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return "divide by zero";
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case 8:
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return "privileged";
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case 9:
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return "load/store alignment";
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case 12:
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return "instr PIF data error";
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case 13:
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return "load/store PIF data error";
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case 14:
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return "instr PIF addr error";
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case 15:
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return "load/store PIF addr error";
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case 16:
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return "instr TLB miss";
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case 17:
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return "instr TLB multi hit";
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case 18:
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return "instr fetch privilege";
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case 20:
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return "inst fetch prohibited";
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case 24:
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return "load/store TLB miss";
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case 25:
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return "load/store TLB multi hit";
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case 26:
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return "load/store privilege";
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case 28:
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return "load prohibited";
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case 29:
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return "store prohibited";
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case 32: case 33: case 34: case 35: case 36: case 37: case 38: case 39:
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return "coprocessor disabled";
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default:
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return "unknown/reserved";
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}
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#else
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ARG_UNUSED(cause_code);
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return "na";
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#endif
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}
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void z_xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
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{
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if (esf) {
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z_xtensa_dump_stack(esf);
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}
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z_fatal_error(reason, esf);
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}
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XTENSA_ERR_NORET void FatalErrorHandler(void)
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{
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z_xtensa_fatal_error(K_ERR_CPU_EXCEPTION, NULL);
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}
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XTENSA_ERR_NORET void ReservedInterruptHandler(unsigned int intNo)
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{
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LOG_ERR("INTENABLE = 0x%x INTERRUPT = 0x%x (%x)",
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get_sreg(INTENABLE), (1 << intNo), intNo);
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z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
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}
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void exit(int return_code)
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{
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#ifdef XT_SIMULATOR
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__asm__ (
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"mov a3, %[code]\n\t"
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"movi a2, %[call]\n\t"
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"simcall\n\t"
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:
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: [code] "r" (return_code), [call] "i" (SYS_exit)
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: "a3", "a2");
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#else
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LOG_ERR("exit(%d)", return_code);
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k_panic();
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#endif
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}
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#ifdef XT_SIMULATOR
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FUNC_NORETURN void z_system_halt(unsigned int reason)
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{
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exit(255 - reason);
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CODE_UNREACHABLE;
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}
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#endif
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