Karsten Koenig 2e61137cc9 arch: riscv: thread: Init soc context on stack ... The optional SOC_CONTEXT carries processor state registers that need to be initialized properly to avoid uninitialized memory read as processor state. In particular on the RV32M1 the extra soc context stores a state for special loop instructions, and loading non zero values will have the core assume it is in a loop. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>		2020-07-13 15:00:19 -05:00
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offsets	kconfig: Rename CONFIG_FP_SHARING to CONFIG_FPU_SHARING	2020-05-08 10:58:33 +02:00
CMakeLists.txt	arch: Simplify private header include path configuration.	2019-11-06 16:07:32 -08:00
cpu_idle.c	riscv: use standard MSTATUS	2020-01-06 13:27:45 -05:00
fatal.c	kernel: remove z_fatal_print()	2019-09-12 05:17:39 -04:00
irq_manage.c	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
irq_offload.c	kernel: rename z_arch_ to arch_	2019-11-07 15:21:46 -08:00
isr.S	kernel: remove legacy fields in _kernel	2020-05-08 17:42:49 +02:00
prep_c.c	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00
reset.S	kconfig: Rename CONFIG_FLOAT to CONFIG_FPU	2020-04-27 19:03:44 +02:00
swap.S	riscv: use standard MSTATUS	2020-01-06 13:27:45 -05:00
thread.c	arch: riscv: thread: Init soc context on stack	2020-07-13 15:00:19 -05:00