zephyr/soc/arm/nuvoton_npcx
Mulin Chao b1214ead19 driver: i2c: npcx: simplify smb bank registers with union
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:

* Common registers, offset 0x00-0x0f, accessible regardless of the value
  of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1

In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.

This CL tries to simplify this by the following steps:

1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
   SMB registers.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-01-11 09:40:36 +01:00
..
common driver: i2c: npcx: simplify smb bank registers with union 2023-01-11 09:40:36 +01:00
npcx7 watchdog: remove Kconfig.defconfig setting of watchdog drivers 2022-08-03 18:30:17 -05:00
npcx9 watchdog: remove Kconfig.defconfig setting of watchdog drivers 2022-08-03 18:30:17 -05:00
CMakeLists.txt soc: arm: Add Nuvoton NPCX7M6FB SoC 2020-08-13 16:42:20 +02:00
Kconfig kconfig: remove Enable from boolean prompts 2022-03-09 15:35:54 +01:00
Kconfig.defconfig soc: arm: Add Nuvoton NPCX7M6FB SoC 2020-08-13 16:42:20 +02:00
Kconfig.soc soc: arm: Add Nuvoton NPCX7M6FB SoC 2020-08-13 16:42:20 +02:00