b23c02f4e0
Fix wrong DCACHE/ICACHE defines. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
497 lines
12 KiB
C
497 lines
12 KiB
C
/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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* Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_CACHE_H_
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#define ZEPHYR_INCLUDE_CACHE_H_
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/**
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* @file
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* @brief cache API interface
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(CONFIG_EXTERNAL_CACHE)
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/*
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* External cache API driver interface mirrored in
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* include/zephyr/drivers/cache.h
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*/
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#if defined(CONFIG_DCACHE)
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extern void cache_data_enable(void);
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extern void cache_data_disable(void);
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extern int cache_data_flush_all(void);
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extern int cache_data_invd_all(void);
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extern int cache_data_flush_and_invd_all(void);
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extern int cache_data_flush_range(void *addr, size_t size);
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extern int cache_data_invd_range(void *addr, size_t size);
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extern int cache_data_flush_and_invd_range(void *addr, size_t size);
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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extern size_t cache_data_line_size_get(void);
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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extern void cache_instr_enable(void);
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extern void cache_instr_disable(void);
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extern int cache_instr_flush_all(void);
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extern int cache_instr_invd_all(void);
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extern int cache_instr_flush_and_invd_all(void);
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extern int cache_instr_flush_range(void *addr, size_t size);
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extern int cache_instr_invd_range(void *addr, size_t size);
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extern int cache_instr_flush_and_invd_range(void *addr, size_t size);
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#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
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extern size_t cache_instr_line_size_get(void);
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_ICACHE */
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#else /* CONFIG_ARCH_CACHE */
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/*
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* Arch cache API interface mirrored in
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* include/zephyr/sys/arch_interface.h
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*/
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#if defined(CONFIG_DCACHE)
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#define cache_data_enable arch_dcache_enable
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#define cache_data_disable arch_dcache_disable
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#define cache_data_flush_all arch_dcache_flush_all
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#define cache_data_invd_all arch_dcache_invd_all
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#define cache_data_flush_and_invd_all arch_dcache_flush_and_invd_all
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#define cache_data_flush_range(addr, size) arch_dcache_flush_range(addr, size)
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#define cache_data_invd_range(addr, size) arch_dcache_invd_range(addr, size)
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#define cache_data_flush_and_invd_range(addr, size) \
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arch_dcache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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#define cache_data_line_size_get arch_dcache_line_size_get
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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#define cache_instr_enable arch_icache_enable
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#define cache_instr_disable arch_icache_disable
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#define cache_instr_flush_all arch_icache_flush_all
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#define cache_instr_invd_all arch_icache_invd_all
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#define cache_instr_flush_and_invd_all arch_icache_flush_and_invd_all
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#define cache_instr_flush_range(addr, size) arch_icache_flush_range(addr, size)
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#define cache_instr_invd_range(addr, size) arch_icache_invd_range(addr, size)
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#define cache_instr_flush_and_invd_range(addr, size) \
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arch_icache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
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#define cache_instr_line_size_get arch_icache_line_size_get
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_ICACHE */
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#endif /* CONFIG_EXTERNAL_CACHE */
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/**
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* @defgroup cache_interface Cache Interface
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* @{
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*/
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/**
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* @cond INTERNAL_HIDDEN
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*
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*/
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#define _CPU DT_PATH(cpus, cpu_0)
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/** @endcond */
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/**
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* @brief Enable the d-cache
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*
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* Enable the data cache
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*
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*/
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static inline void sys_cache_data_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_enable();
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#endif
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}
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/**
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* @brief Disable the d-cache
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*
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* Disable the data cache
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*
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*/
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static inline void sys_cache_data_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_disable();
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#endif
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}
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/**
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* @brief Enable the i-cache
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*
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* Enable the instruction cache
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*
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*/
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static inline void sys_cache_instr_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_enable();
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#endif
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}
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/**
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* @brief Disable the i-cache
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*
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* Disable the instruction cache
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*
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*/
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static inline void sys_cache_instr_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_disable();
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#endif
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}
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/**
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* @brief Flush the d-cache
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*
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* Flush the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_data_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush the i-cache
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*
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* Flush the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate the d-cache
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*
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* Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_data_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate the i-cache
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*
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* Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate the d-cache
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*
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* Flush and Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_data_flush_and_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_and_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate the i-cache
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*
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* Flush and Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_flush_and_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_and_invd_all();
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#endif
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return -ENOTSUP;
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}
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/**
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* @brief Flush an address range in the d-cache
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*
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* Flush the specified address range of the data cache.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall int sys_cache_data_flush_range(void *addr, size_t size);
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static inline int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush an address range in the i-cache
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*
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* Flush the specified address range of the instruction cache.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_flush_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate an address range in the d-cache
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*
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* Invalidate the specified address range of the data cache.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall int sys_cache_data_invd_range(void *addr, size_t size);
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static inline int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Invalidate an address range in the i-cache
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*
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* Invalidate the specified address range of the instruction cache.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate an address range in the d-cache
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*
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* Flush and Invalidate the specified address range of the data cache.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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__syscall int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
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static inline int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_and_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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* @brief Flush and Invalidate an address range in the i-cache
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*
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* Flush and Invalidate the specified address range of the instruction cache.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_and_invd_range(addr, size);
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#endif
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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/**
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*
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* @brief Get the the d-cache line size.
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*
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* The API is provided to get the data cache line.
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*
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* The cache line size is calculated (in order of priority):
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*
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* - At run-time when @kconfig{CONFIG_DCACHE_LINE_SIZE_DETECT} is set.
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* - At compile time using the value set in @kconfig{CONFIG_DCACHE_LINE_SIZE}.
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* - At compile time using the `d-cache-line-size` CPU0 property of the DT.
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* - 0 otherwise
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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static inline size_t sys_cache_data_line_size_get(void)
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{
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#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
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return cache_data_line_size_get();
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#elif (CONFIG_DCACHE_LINE_SIZE != 0)
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return CONFIG_DCACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(_CPU, d_cache_line_size, 0);
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#endif
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}
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/**
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*
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* @brief Get the the i-cache line size.
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*
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* The API is provided to get the instruction cache line.
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*
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* The cache line size is calculated (in order of priority):
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*
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* - At run-time when @kconfig{CONFIG_ICACHE_LINE_SIZE_DETECT} is set.
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* - At compile time using the value set in @kconfig{CONFIG_ICACHE_LINE_SIZE}.
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* - At compile time using the `i-cache-line-size` CPU0 property of the DT.
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* - 0 otherwise
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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static inline size_t sys_cache_instr_line_size_get(void)
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{
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#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
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return cache_instr_line_size_get();
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#elif (CONFIG_ICACHE_LINE_SIZE != 0)
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return CONFIG_ICACHE_LINE_SIZE;
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#else
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return DT_PROP_OR(_CPU, i_cache_line_size, 0);
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#endif
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}
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#ifdef CONFIG_LIBMETAL
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static inline void sys_cache_flush(void *addr, size_t size)
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{
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sys_cache_data_flush_range(addr, size);
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}
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#endif
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#include <syscalls/cache.h>
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#ifdef __cplusplus
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}
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#endif
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/**
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* @}
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*/
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#endif /* ZEPHYR_INCLUDE_CACHE_H_ */
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