2176ca9f9b
This commit updates the device tree and memory header file for the Intel cAVS 2.5 platform to define the LSBPM and HSBPM registers. Changes include: - Added node definitions for 'lsbpm' and 'hsbpm' in intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi - Updated adsp_memory.h Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
404 lines
8 KiB
Plaintext
404 lines
8 KiB
Plaintext
/*
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* Copyright (c) 2019,2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/intel/intel_adsp_cavs.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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cpu-power-states = <&d3>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <1>;
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cpu-power-states = <&d3>;
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};
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power-states {
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/* PM_STATE_SOFT_OFF can be entered only by calling
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* pm_state_force. The procedure is triggered by IPC
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* from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2147483647>;
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exit-latency-us = <0>;
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};
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};
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};
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sram0: memory@be000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe000000 DT_SIZE_K(1920)>;
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};
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sram1: memory@be800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe800000 DT_SIZE_K(64)>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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#clock-cells = <0>;
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};
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audioclk: audio-clock {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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#clock-cells = <0>;
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};
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pllclk: pll-clock {
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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#clock-cells = <0>;
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};
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clkctl: clkctl {
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compatible = "intel,adsp-shim-clkctl";
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adsp-clkctl-clk-wovcro = <0>;
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adsp-clkctl-clk-lpro = <1>;
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adsp-clkctl-clk-hpro = <2>;
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adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
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adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
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adsp-clkctl-freq-default = <2>;
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adsp-clkctl-freq-lowest = <0>;
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wovcro-supported;
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};
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IMR1: memory@b0000000 {
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compatible = "intel,adsp-imr";
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reg = <0xB0000000 DT_SIZE_M(16)>;
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block-size = <0x1000>;
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zephyr,memory-region = "IMR1";
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};
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soc {
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lsbpm: lsbpm@71d50 {
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compatible = "intel,adsp-lsbpm";
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reg = <0x71d50 0x10>;
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};
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hsbpm: hsbpm@71d10 {
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compatible = "intel,adsp-hsbpm";
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reg = <0x71d10 0x10>;
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};
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shim: shim@71f00 {
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compatible = "intel,adsp-shim";
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reg = <0x71f00 0x100>;
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};
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mem_window0: mem_window@71a00 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a00 0x8>;
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offset = <0x4000>;
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memory = <&sram0>;
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initialize;
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read-only;
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};
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mem_window1: mem_window@71a08 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a08 0x8>;
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memory = <&sram0>;
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};
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mem_window2: mem_window@71a10 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a10 0x8>;
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memory = <&sram0>;
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};
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mem_window3: mem_window@71a18 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a18 0x8>;
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memory = <&sram0>;
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read-only;
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};
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timer: timer {
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compatible = "intel,adsp-timer";
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syscon = <&shim>;
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};
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sspbase: ssp_base@71c00 {
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compatible = "intel,cavs-sspbase";
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reg = <0x71c00 0x100>;
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};
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l2lm: l2lm@71d00 {
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compatible = "intel,cavs-l2lm";
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reg = <0x71d00 0x20>;
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};
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adsp_host_ipc: cavs_host_ipc@71e00 {
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compatible = "intel,adsp-host-ipc";
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reg = <0x71e00 0x30>;
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interrupts = <7 0 0>;
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interrupt-parent = <&cavs_intc0>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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cavs_intc0: cavs@78800 {
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compatible = "intel,cavs-intc";
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reg = <0x78800 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc1: cavs@78810 {
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compatible = "intel,cavs-intc";
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reg = <0x78810 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc2: cavs@78820 {
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compatible = "intel,cavs-intc";
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reg = <0x78820 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc3: cavs@78830 {
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compatible = "intel,cavs-intc";
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reg = <0x78830 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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};
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adsp_idc: idc@1200 {
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compatible = "intel,adsp-idc";
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reg = <0x1200 0x80>;
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs_intc0>;
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};
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tlb: tlb@3000 {
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compatible = "intel,adsp-tlb";
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reg = <0x3000 0x1000>;
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paddr-size = <11>;
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};
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dmic0: dmic0@10000 {
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compatible = "intel,dai-dmic";
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reg = <0x10000 0x8000>;
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shim = <0x71E80>;
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fifo = <0x0008>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&cavs_intc3>;
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};
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dmic1: dmic1@10000 {
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compatible = "intel,dai-dmic";
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reg = <0x10000 0x8000>;
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shim = <0x71E80>;
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fifo = <0x0108>;
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interrupts = <0x09 0 0>;
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interrupt-parent = <&cavs_intc3>;
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};
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/*
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* FIXME this is modeling individual alh channels/instances
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* with node labels, which has problems. A better representation
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* is discussed here:
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*
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* https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009
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*/
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alh0: alh0@71000 {
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compatible = "intel,alh-dai";
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reg = <0x00071000 0x00071200>;
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status = "okay";
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};
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alh1: alh1@71000 {
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compatible = "intel,alh-dai";
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reg = <0x00071000 0x00071200>;
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status = "okay";
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};
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ssp0: ssp@77000 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00077000 0x200
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0x00078C00 0x008>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&cavs_intc3>;
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dmas = <&lpgpdma0 2
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&lpgpdma0 3>;
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dma-names = "tx", "rx";
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ssp-index = <0>;
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status = "okay";
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ssp00: ssp@0 {
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compatible = "intel,ssp-dai";
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reg = <0x0>;
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status = "okay";
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};
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};
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ssp1: ssp@77200 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00077200 0x200
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0x00078C00 0x008>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&cavs_intc3>;
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dmas = <&lpgpdma0 4
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&lpgpdma0 5>;
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dma-names = "tx", "rx";
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ssp-index = <1>;
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status = "okay";
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ssp10: ssp@10 {
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compatible = "intel,ssp-dai";
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reg = <0x10>;
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status = "okay";
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};
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};
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ssp2: ssp@77400 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00077400 0x200
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0x00078C00 0x008>;
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interrupts = <0x02 0 0>;
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interrupt-parent = <&cavs_intc3>;
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dmas = <&lpgpdma0 6
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&lpgpdma0 7>;
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dma-names = "tx", "rx";
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ssp-index = <2>;
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status = "okay";
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ssp20: ssp@20 {
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compatible = "intel,ssp-dai";
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reg = <0x20>;
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status = "okay";
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};
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};
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};
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hdas {
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#address-cells = <1>;
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#size-cells = <0>;
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hda0: hda@0 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0>;
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};
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hda1: hda@1 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <1>;
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};
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hda2: hda@2 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <2>;
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};
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hda3: hda@3 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <3>;
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};
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hda4: hda@4 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <4>;
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};
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hda5: hda@5 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <5>;
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};
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hda6: hda@6 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <6>;
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};
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hda7: hda@7 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <7>;
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};
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hda8: hda@8 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <8>;
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};
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hda9: hda@9 {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <9>;
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};
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hda10: hda@a {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0a>;
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};
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hda11: hda@b {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0b>;
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};
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hda12: hda@c {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0c>;
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};
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hda13: hda@d {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0d>;
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};
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hda14: hda@e {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0e>;
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};
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hda15: hda@f {
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compatible = "intel,hda-dai";
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status = "okay";
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reg = <0x0f>;
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};
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};
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};
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