1c5f924628
Added i-cache-line-size and d-cache-line-size values to device tree for cavs and ace platforms. These values are used by sys_cache_instr_line_size_get and sys_cache_data_line_size_get functions. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
166 lines
3.3 KiB
Plaintext
166 lines
3.3 KiB
Plaintext
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/intel/intel_adsp_cavs.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <1>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <3>;
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};
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};
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sram0: memory@be000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe000000 DT_SIZE_K(3008)>;
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};
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sram1: memory@be800000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe800000 DT_SIZE_K(64)>;
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};
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clkctl: clkctl {
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compatible = "intel,adsp-shim-clkctl";
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adsp-clkctl-clk-lpro = <0>;
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adsp-clkctl-clk-hpro = <1>;
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adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
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adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
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adsp-clkctl-freq-default = <1>;
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adsp-clkctl-freq-lowest = <0>;
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};
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soc {
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shim: shim@71f00 {
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compatible = "intel,adsp-shim";
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reg = <0x71f00 0x100>;
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};
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mem_window0: mem_window@71a00 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a00 0x8>;
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offset = <0x4000>;
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memory = <&sram0>;
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initialize;
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read-only;
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};
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mem_window1: mem_window@71a08 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a08 0x8>;
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memory = <&sram0>;
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};
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mem_window2: mem_window@71a10 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a10 0x8>;
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memory = <&sram0>;
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};
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mem_window3: mem_window@71a18 {
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compatible = "intel,adsp-mem-window";
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reg = <0x71a18 0x8>;
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memory = <&sram0>;
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read-only;
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};
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timer: timer {
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compatible = "intel,adsp-timer";
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syscon = <&shim>;
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};
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l2lm: l2lm@71d00 {
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compatible = "intel,cavs-l2lm";
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reg = <0x71d00 0x20>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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adsp_host_ipc: cavs_host_ipc@71e00 {
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compatible = "intel,adsp-host-ipc";
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reg = <0x71e00 0x30>;
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interrupts = <7 0 0>;
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interrupt-parent = <&cavs_intc0>;
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};
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cavs_intc0: cavs@78800 {
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compatible = "intel,cavs-intc";
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reg = <0x78800 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc1: cavs@78810 {
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compatible = "intel,cavs-intc";
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reg = <0x78810 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc2: cavs@78820 {
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compatible = "intel,cavs-intc";
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reg = <0x78820 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs_intc3: cavs@78830 {
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compatible = "intel,cavs-intc";
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reg = <0x78830 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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};
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adsp_idc: idc@1200 {
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compatible = "intel,adsp-idc";
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reg = <0x1200 0x80>;
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interrupts = <8 0 0>;
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interrupt-parent = <&cavs_intc0>;
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};
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};
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};
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