6205f82d4f
This commit updates the device tree and memory header file for the Intel MTPM 1.5 platform to define the LSBPM and HSBPM registers. Changes include: - Added node definitions for 'lsbpm' and 'hsbpm' in intel_adsp_ace15_mtpm.dtsi - Updated adsp_memory.h Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
681 lines
14 KiB
Plaintext
681 lines
14 KiB
Plaintext
/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <0>;
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cpu-power-states = <&d0i3 &d3>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <1>;
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cpu-power-states = <&d0i3 &d3>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <2>;
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cpu-power-states = <&d0i3 &d3>;
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};
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power-states {
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d0i3: idle {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <200>;
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exit-latency-us = <100>;
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};
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/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
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* The procedure is triggered by IPC from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <0>;
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exit-latency-us = <0>;
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status = "disabled";
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};
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};
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};
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sram0: memory@a0020000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0020000 DT_SIZE_K(2816)>;
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};
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sram0virtual: virtualmemory@a0020000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0020000 DT_SIZE_K(8192)>;
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};
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sram1: memory@a0000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0000000 DT_SIZE_K(64)>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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#clock-cells = <0>;
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};
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clkctl: clkctl {
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compatible = "intel,adsp-shim-clkctl";
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adsp-clkctl-clk-wovcro = <0>;
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adsp-clkctl-clk-ipll = <1>;
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adsp-clkctl-freq-enc = <0xc 0x4>;
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adsp-clkctl-freq-mask = <0x0 0x0>;
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adsp-clkctl-freq-default = <1>;
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adsp-clkctl-freq-lowest = <0>;
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wovcro-supported;
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};
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audioclk: audio-clock {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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#clock-cells = <0>;
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};
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pllclk: pll-clock {
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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#clock-cells = <0>;
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};
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IMR1: memory@A1000000 {
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compatible = "intel,adsp-imr";
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reg = <0xA1000000 DT_SIZE_M(16)>;
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block-size = <0x1000>;
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zephyr,memory-region = "IMR1";
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};
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soc {
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lsbpm: lsbpm@71d80 {
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compatible = "intel,adsp-lsbpm";
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reg = <0x71d80 0x0008>;
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};
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hsbpm: hsbpm@17a800 {
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compatible = "intel,adsp-hsbpm";
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reg = <0x17a800 0x0008>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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dmic0: dmic0@10000 {
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compatible = "intel,dai-dmic";
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reg = <0x10000 0x8000>;
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shim = <0xC000>;
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fifo = <0x0008>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&ace_intc>;
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power-domain = <&hub_ulp_domain>;
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};
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dmic1: dmic1@10000 {
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compatible = "intel,dai-dmic";
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reg = <0x10000 0x8000>;
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shim = <0xC000>;
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fifo = <0x0108>;
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interrupts = <0x09 0 0>;
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interrupt-parent = <&ace_intc>;
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power-domain = <&hub_ulp_domain>;
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};
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/*
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* FIXME this is modeling individual alh channels/instances
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* with node labels, which has problems. A better representation
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* is discussed here:
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*
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* https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009
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*
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* The hardware actually supports 16 ALH streams/FIFOs. Below description does
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* not fully represent hardware capabilities and is expected to be modified.
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*/
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alh0: alh0@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh1: alh1@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh2: alh2@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh3: alh3@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh4: alh4@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh5: alh5@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh6: alh6@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh7: alh7@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh8: alh8@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh9: alh9@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh10: alh10@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh11: alh11@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh12: alh12@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh13: alh13@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh14: alh14@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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alh15: alh15@24400 {
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compatible = "intel,alh-dai";
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reg = <0x00024400 0x00024600>;
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status = "okay";
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};
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sspbase: ssp_base@28800 {
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compatible = "intel,ssp-sspbase";
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reg = <0x28800 0x1000>;
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};
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ssp0: ssp@28000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ssp";
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reg = <0x00028000 0x1000
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0x00079C00 0x200>;
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interrupts = <0x00 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&lpgpdma0 2
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&lpgpdma0 3>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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ssp-index = <0>;
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status = "okay";
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ssp00: ssp@0 {
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compatible = "intel,ssp-dai";
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status = "okay";
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reg = <0x0>;
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};
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};
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ssp1: ssp@29000 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00029000 0x1000
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0x00079C00 0x200>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&lpgpdma0 4
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&lpgpdma0 5>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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ssp-index = <1>;
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status = "okay";
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ssp10: ssp@10 {
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compatible = "intel,ssp-dai";
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status = "okay";
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reg = <0x10>;
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};
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};
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ssp2: ssp@2a000 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0002a000 0x1000
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0x00079C00 0x200>;
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interrupts = <0x02 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&lpgpdma0 6
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&lpgpdma0 7>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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ssp-index = <2>;
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status = "okay";
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ssp20: ssp@20 {
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compatible = "intel,ssp-dai";
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status = "okay";
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reg = <0x20>;
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};
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};
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mem_window0: mem_window@70200 {
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compatible = "intel,adsp-mem-window";
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reg = <0x70200 0x8>;
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offset = <0x4000>;
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memory = <&sram0>;
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initialize;
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read-only;
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};
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mem_window1: mem_window@70208 {
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compatible = "intel,adsp-mem-window";
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reg = <0x70208 0x8>;
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memory = <&sram0>;
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};
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mem_window2: mem_window@70210 {
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compatible = "intel,adsp-mem-window";
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reg = <0x70210 0x8>;
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memory = <&sram0>;
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};
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mem_window3: mem_window@70218 {
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compatible = "intel,adsp-mem-window";
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reg = <0x70218 0x8>;
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memory = <&sram0>;
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read-only;
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};
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adsp_idc: ace_idc@70400 {
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compatible = "intel,adsp-idc";
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reg = <0x70400 0x0400>;
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interrupts = <24 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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dfpmcch: dfpmcch@71ac0 {
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compatible = "intel,adsp-dfpmcch";
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reg = <0x00071ac0 0x40>;
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};
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dfpmccu: dfpmccu@71b00 {
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compatible = "intel,adsp-dfpmccu";
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reg = <0x71b00 0x100>;
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hub_ulp_domain: hub_ulp_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <15>;
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};
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ml1_domain: ml1_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <13>;
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};
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ml0_domain: ml0_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <12>;
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};
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io3_domain: io3_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <11>;
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};
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io2_domain: io2_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <10>;
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};
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io1_domain: io1_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <9>;
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};
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io0_domain: io0_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <8>;
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};
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hub_hp_domain: hub_hp_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <6>;
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};
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hst_domain: hst_domain {
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compatible = "intel,adsp-power-domain";
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bit-position = <4>;
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};
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};
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ace_comm_widget: ace_comm_widget@71c00 {
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compatible = "intel,adsp-communication-widget";
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reg = <0x00071c00 0x100>;
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interrupts = <0x19 0 0>;
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interrupt-parent = <&ace_intc>;
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status = "okay";
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};
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shim: shim@71f00 {
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compatible = "intel,adsp-shim";
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reg = <0x71f00 0x100>;
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};
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tts: tts@72000 {
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compatible = "intel,adsp-tts";
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reg = <0x72000 0x70>;
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status = "okay";
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};
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ace_rtc_counter: ace_rtc_counter@72008 {
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compatible = "intel,ace-rtc-counter";
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reg = <0x72008 0x0064>;
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};
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ace_timestamp: ace_timestamp@72040 {
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compatible = "intel,ace-timestamp";
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reg = <0x72040 0x0032>;
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};
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ace_art_counter: ace_art_counter@72058 {
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compatible = "intel,ace-art-counter";
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reg = <0x72058 0x0064>;
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};
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hda_link_out: dma@72400 {
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compatible = "intel,adsp-hda-link-out";
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#dma-cells = <1>;
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reg = <0x00072400 0x20>;
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dma-channels = <9>;
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dma-buf-addr-alignment = <128>;
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dma-buf-size-alignment = <32>;
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dma-copy-alignment = <16>;
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power-domain = <&io0_domain>;
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status = "okay";
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};
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hda_link_in: dma@72600 {
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compatible = "intel,adsp-hda-link-in";
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#dma-cells = <1>;
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reg = <0x00072600 0x20>;
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dma-channels = <10>;
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dma-buf-addr-alignment = <128>;
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dma-buf-size-alignment = <32>;
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dma-copy-alignment = <16>;
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power-domain = <&io0_domain>;
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status = "okay";
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};
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hda_host_out: dma@72800 {
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compatible = "intel,adsp-hda-host-out";
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#dma-cells = <1>;
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reg = <0x00072800 0x40>;
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dma-channels = <9>;
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dma-buf-addr-alignment = <128>;
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dma-buf-size-alignment = <32>;
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dma-copy-alignment = <16>;
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power-domain = <&hst_domain>;
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interrupts = <13 0 0>;
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interrupt-parent = <&ace_intc>;
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status = "okay";
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};
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hda_host_in: dma@72c00 {
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compatible = "intel,adsp-hda-host-in";
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#dma-cells = <1>;
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reg = <0x00072c00 0x40>;
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dma-channels = <10>;
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dma-buf-addr-alignment = <128>;
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dma-buf-size-alignment = <32>;
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dma-copy-alignment = <16>;
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power-domain = <&hst_domain>;
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interrupts = <12 0 0>;
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interrupt-parent = <&ace_intc>;
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status = "okay";
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};
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adsp_host_ipc: ace_host_ipc@73000 {
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compatible = "intel,adsp-host-ipc";
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status = "okay";
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reg = <0x73000 0x30>;
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interrupts = <0 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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/* This is actually an array of per-core designware
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* controllers, but the special setup and extra
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* masking layer makes it easier for MTL to handle
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* this internally.
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*/
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ace_intc: ace_intc@7ac00 {
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compatible = "intel,ace-intc";
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reg = <0x7ac00 0xc00>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <4 0 0>;
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num-irqs = <28>;
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interrupt-parent = <&core_intc>;
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};
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lpgpdma0: dma@7c000 {
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compatible = "intel,adsp-gpdma";
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#dma-cells = <1>;
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reg = <0x0007c000 0x1000>;
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shim = <0x0007c800 0x1000>;
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interrupts = <17 0 0>;
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interrupt-parent = <&ace_intc>;
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dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
status = "okay";
|
|
power-domain = <&hub_ulp_domain>;
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
lpgpdma1: dma@7d000 {
|
|
compatible = "intel,adsp-gpdma";
|
|
#dma-cells = <1>;
|
|
reg = <0x0007d000 0x1000>;
|
|
shim = <0x0007d800 0x1000>;
|
|
interrupts = <0x20 0 0>;
|
|
interrupt-parent = <&core_intc>;
|
|
dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
status = "okay";
|
|
power-domain = <&io0_domain>;
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
lpgpdma2: dma@7e000 {
|
|
compatible = "intel,adsp-gpdma";
|
|
#dma-cells = <1>;
|
|
reg = <0x0007e000 0x1000>;
|
|
shim = <0x0007e800 0x1000>;
|
|
interrupts = <0x25 0 0>;
|
|
interrupt-parent = <&core_intc>;
|
|
dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
power-domain = <&io0_domain>;
|
|
status = "okay";
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
sha: adsp-sha@17df00 {
|
|
compatible = "intel,adsp-sha";
|
|
reg = <0x17df00 0xd0>;
|
|
};
|
|
|
|
tlb: tlb@17e000 {
|
|
compatible = "intel,adsp-mtl-tlb";
|
|
reg = <0x17e000 0x1000>;
|
|
paddr-size = <12>;
|
|
exec-bit-idx = <14>;
|
|
write-bit-idx= <15>;
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "intel,adsp-timer";
|
|
syscon = <&tts>;
|
|
};
|
|
};
|
|
|
|
hdas {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hda0: hda@0 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0>;
|
|
};
|
|
hda1: hda@1 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <1>;
|
|
};
|
|
hda2: hda@2 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <2>;
|
|
};
|
|
hda3: hda@3 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <3>;
|
|
};
|
|
hda4: hda@4 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <4>;
|
|
};
|
|
hda5: hda@5 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <5>;
|
|
};
|
|
hda6: hda@6 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <6>;
|
|
};
|
|
hda7: hda@7 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <7>;
|
|
};
|
|
hda8: hda@8 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <8>;
|
|
};
|
|
hda9: hda@9 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <9>;
|
|
};
|
|
hda10: hda@a {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0a>;
|
|
};
|
|
hda11: hda@b {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0b>;
|
|
};
|
|
hda12: hda@c {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0c>;
|
|
};
|
|
hda13: hda@d {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0d>;
|
|
};
|
|
hda14: hda@e {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0e>;
|
|
};
|
|
hda15: hda@f {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0f>;
|
|
};
|
|
hda16: hda@10 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x10>;
|
|
};
|
|
hda17: hda@11 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x11>;
|
|
};
|
|
hda18: hda@12 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x12>;
|
|
};
|
|
};
|
|
};
|