81bf4f98f7
This commit introduces the 1-wire master driver for maxim ds2485. The ds2485 master has nearly the same (1-wire) feature set and i2c-interface as the ds2477. Therefore the common parts are extracted, but to avoid any nda troubles only the ds2485 specific part is included. Compared to older 1-wire masters, the ds2485 supports higher level commands, supporting multi byte operations, search next, automatic crc calculation. In this driver only basic read and write operations are supported, further hardware features are not yet utilized by the driver. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* Copyright (c) 2022 Thomas Stranger
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT maxim_ds2485
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/**
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* @brief Driver for the Maxim ds2485 1-Wire Master
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*/
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#include "w1_ds2477_85_common.h"
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/w1.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(w1_ds2485, CONFIG_W1_LOG_LEVEL);
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/* upper limits; guaranteed over operating temperature range */
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#define DS2485_T_OSCWUP_us 1000U
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#define DS2485_T_OP_us 400U
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#define DS2485_T_SEQ_us 10U
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int ds2485_w1_script_cmd(const struct device *dev, int w1_delay_us, uint8_t w1_cmd,
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const uint8_t *tx_buf, const uint8_t tx_len,
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uint8_t *rx_buf, uint8_t rx_len)
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{
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const struct w1_ds2477_85_config *cfg = dev->config;
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uint8_t i2c_len = 3 + tx_len;
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uint8_t tx_bytes[3 + SCRIPT_WR_LEN] = {
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CMD_W1_SCRIPT, tx_len + CMD_W1_SCRIPT_LEN, w1_cmd
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};
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uint8_t rx_bytes[3];
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struct i2c_msg rx_msg[2] = {
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{
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.buf = rx_bytes,
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.len = (CMD_W1_SCRIPT_LEN + CMD_OVERHEAD_LEN),
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.flags = I2C_MSG_READ,
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},
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{
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.buf = rx_buf,
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.len = rx_len,
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.flags = (I2C_MSG_READ | I2C_MSG_STOP),
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},
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};
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int ret;
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__ASSERT_NO_MSG(tx_len <= SCRIPT_WR_LEN);
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memcpy(&tx_bytes[3], tx_buf, tx_len);
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ret = i2c_write_dt(&cfg->i2c_spec, tx_bytes, i2c_len);
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if (ret < 0) {
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return ret;
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}
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k_usleep(DS2485_T_OP_us + DS2485_T_SEQ_us + w1_delay_us);
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ret = i2c_transfer_dt(&cfg->i2c_spec, rx_msg, 2);
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if (ret < 0) {
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LOG_ERR("scripts_cmd fail: ret: %x", ret);
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return ret;
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}
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if ((rx_bytes[0] != (rx_len + 2)) || (rx_bytes[2] != w1_cmd)) {
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LOG_ERR("scripts_cmd fail: response: %x,%x:",
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rx_bytes[0], rx_bytes[2]);
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return -EIO;
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}
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return rx_bytes[1];
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}
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static int w1_ds2485_init(const struct device *dev)
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{
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const struct w1_ds2477_85_config *cfg = dev->config;
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if (!device_is_ready(cfg->i2c_spec.bus)) {
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LOG_ERR("%s is not ready", cfg->i2c_spec.bus->name);
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return -ENODEV;
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}
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if (ds2477_85_reset_master(dev)) {
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return -EIO;
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}
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k_usleep(DS2485_T_OSCWUP_us);
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return w1_ds2477_85_init(dev);
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}
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static const struct w1_driver_api w1_ds2485_driver_api = {
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.reset_bus = ds2477_85_reset_bus,
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.read_bit = ds2477_85_read_bit,
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.write_bit = ds2477_85_write_bit,
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.read_byte = ds2477_85_read_byte,
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.write_byte = ds2477_85_write_byte,
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.read_block = ds2477_85_read_block,
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.write_block = ds2477_85_write_block,
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.configure = ds2477_85_configure,
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};
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#define W1_DS2485_INIT(inst) \
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static const struct w1_ds2477_85_config w1_ds2477_85_cfg_##inst = \
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W1_DS2477_85_DT_CONFIG_INST_GET(inst, DS2485_T_OP_us, \
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DS2485_T_SEQ_us, \
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ds2485_w1_script_cmd); \
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\
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static struct w1_ds2477_85_data w1_ds2477_85_data_##inst = {}; \
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DEVICE_DT_INST_DEFINE(inst, &w1_ds2485_init, NULL, \
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&w1_ds2477_85_data_##inst, \
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&w1_ds2477_85_cfg_##inst, POST_KERNEL, \
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CONFIG_W1_INIT_PRIORITY, &w1_ds2485_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(W1_DS2485_INIT)
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