64cc0764ee
Recent changes to the arm64 MMU code mean that you can no longer map R/O memory as R/W. Mapping R/W memory now causes a cache invalidation instruction (DC IVAC) that requires write permissions or else a fault is generated. Modify ivshmem-v2 to map each R/O and R/W section individually Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_
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#define ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_
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#include <zephyr/drivers/pcie/pcie.h>
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#ifdef CONFIG_IVSHMEM_DOORBELL
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#include <zephyr/drivers/pcie/msi.h>
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#endif
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#define PCIE_CONF_CMDSTAT_INTX_DISABLE 0x0400
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#define PCIE_CONF_INTR_PIN(x) (((x) >> 8) & 0xFFu)
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#define IVSHMEM_CFG_ID 0x00
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#define IVSHMEM_CFG_NEXT_CAP 0x01
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#define IVSHMEM_CFG_LENGTH 0x02
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#define IVSHMEM_CFG_PRIV_CNTL 0x03
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#define IVSHMEM_PRIV_CNTL_ONESHOT_INT BIT(0)
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#define IVSHMEM_CFG_STATE_TAB_SZ 0x04
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#define IVSHMEM_CFG_RW_SECTION_SZ 0x08
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#define IVSHMEM_CFG_OUTPUT_SECTION_SZ 0x10
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#define IVSHMEM_CFG_ADDRESS 0x18
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#define IVSHMEM_INT_ENABLE BIT(0)
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#define IVSHMEM_PCIE_REG_BAR_IDX 0
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#define IVSHMEM_PCIE_MSI_X_BAR_IDX 1
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#define IVSHMEM_PCIE_SHMEM_BAR_IDX 2
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#define PCIE_INTX_PIN_MIN 1
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#define PCIE_INTX_PIN_MAX 4
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#define INTX_IRQ_UNUSED UINT32_MAX
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struct ivshmem_param {
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const struct device *dev;
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struct k_poll_signal *signal;
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uint8_t vector;
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};
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struct ivshmem {
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DEVICE_MMIO_RAM;
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struct pcie_dev *pcie;
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uintptr_t shmem;
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size_t size;
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#ifdef CONFIG_IVSHMEM_DOORBELL
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msi_vector_t vectors[CONFIG_IVSHMEM_MSI_X_VECTORS];
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struct ivshmem_param params[CONFIG_IVSHMEM_MSI_X_VECTORS];
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uint16_t n_vectors;
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#endif
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#ifdef CONFIG_IVSHMEM_V2
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bool ivshmem_v2;
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uint32_t max_peers;
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size_t rw_section_size;
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size_t output_section_size;
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uintptr_t state_table_shmem;
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uintptr_t rw_section_shmem;
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uintptr_t output_section_shmem[CONFIG_IVSHMEM_V2_MAX_PEERS];
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#endif
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};
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struct ivshmem_reg {
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uint32_t int_mask;
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uint32_t int_status;
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uint32_t iv_position;
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uint32_t doorbell;
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};
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#ifdef CONFIG_IVSHMEM_V2
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struct ivshmem_v2_reg {
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uint32_t id;
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uint32_t max_peers;
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uint32_t int_control;
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uint32_t doorbell;
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uint32_t state;
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};
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struct ivshmem_cfg {
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struct intx_info {
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uint32_t irq;
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uint32_t priority;
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uint32_t flags;
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} intx_info[PCIE_INTX_PIN_MAX];
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};
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#endif /* CONFIG_IVSHMEM_V2 */
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#define IVSHMEM_GEN_DOORBELL(i, v) ((i << 16) | (v & 0xFFFF))
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#endif /* ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_ */
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