da639954c1
Add common layer of UHC API and MAX3421E host controller driver. This implements the bare minimum necessary to communicate with one peripheral device. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
214 lines
6.7 KiB
C
214 lines
6.7 KiB
C
/*
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* Copyright (c) 2022 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_UHC_MAX3421E_H
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#define ZEPHYR_INCLUDE_UHC_MAX3421E_H
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#include <zephyr/sys/util_macro.h>
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#define MAX3421E_MAX_EP_SIZE 64U
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/* SPI command byte format macros */
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#define MAX3421E_CMD_REG_SHIFT 3U
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#define MAX3421E_CMD_DIR_WR BIT(1)
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#define MAX3421E_CMD_DIR_RD 0U
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#define MAX3421E_CMD_SPI_READ(reg) \
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(((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_RD)
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#define MAX3421E_CMD_SPI_WRITE(reg) \
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(((reg) << MAX3421E_CMD_REG_SHIFT) | MAX3421E_CMD_DIR_WR)
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/* Below are all the register definitions for the host mode. */
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/* Register RCVFIFO */
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#define MAX3421E_REG_RCVFIFO 1U
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/* Register SNDFIFO */
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#define MAX3421E_REG_SNDFIFO 2U
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/* Register SUDFIFO */
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#define MAX3421E_REG_SUDFIFO 4U
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/* Register RCVBC */
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#define MAX3421E_REG_RCVBC 6U
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#define MAX3421E_RCVBC_MAX 0x7FU
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/* Register SNDBC */
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#define MAX3421E_REG_SNDBC 7U
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#define MAX3421E_SNDBC_MAX 0x7FU
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/* Register USBIRQ */
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#define MAX3421E_REG_USBIRQ 13U
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#define MAX3421E_VBUSIRQ BIT(6)
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#define MAX3421E_NOVBUSIRQ BIT(5)
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#define MAX3421E_OSCOKIRQ BIT(0)
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/* Register USBIEN */
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#define MAX3421E_REG_USBIEN 14U
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#define MAX3421E_VBUSIE BIT(6)
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#define MAX3421E_NOVBUSIE BIT(5)
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#define MAX3421E_OSCOKIE BIT(0)
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/* Register USBCTL */
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#define MAX3421E_REG_USBCTL 15U
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#define MAX3421E_CHIPRES BIT(5)
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#define MAX3421E_PWRDOWN BIT(4)
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/* Register CPUCTL */
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#define MAX3421E_REG_CPUCTL 16U
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#define MAX3421E_PULSEWID1 BIT(7)
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#define MAX3421E_PULSEWID0 BIT(6)
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#define MAX3421E_IE BIT(0)
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/* Register PINCTL */
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#define MAX3421E_REG_PINCTL 17U
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#define MAX3421E_FDUPSPI BIT(4)
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#define MAX3421E_INTLEVEL BIT(3)
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#define MAX3421E_POSINT BIT(2)
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#define MAX3421E_GPXB BIT(1)
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#define MAX3421E_GPXA BIT(0)
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/* Register REVISION */
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#define MAX3421E_REG_REVISION 18U
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/* Register IOPINS1, IOPINS2, GPINIRQ, GPINIEN, GPINPOL */
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#define MAX3421E_REG_IOPINS1 20U
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#define MAX3421E_REG_IOPINS2 21U
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#define MAX3421E_REG_GPINIRQ 22U
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#define MAX3421E_REG_GPINIE 23U
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#define MAX3421E_REG_GPINPOL 24U
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/* Register HIRQ and HIEN */
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#define MAX3421E_REG_HIRQ 25U
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#define MAX3421E_REG_HIEN 26U
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#define MAX3421E_HXFRDN BIT(7)
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#define MAX3421E_FRAME BIT(6)
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#define MAX3421E_CONDET BIT(5)
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#define MAX3421E_SUSDN BIT(4)
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#define MAX3421E_SNDBAV BIT(3)
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#define MAX3421E_RCVDAV BIT(2)
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#define MAX3421E_RWU BIT(1)
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#define MAX3421E_BUSEVENT BIT(0)
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/* Register MODE */
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#define MAX3421E_REG_MODE 27U
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#define MAX3421E_DPPULLDN BIT(7)
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#define MAX3421E_DMPULLDN BIT(6)
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#define MAX3421E_DELAYISO BIT(5)
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#define MAX3421E_SEPIRQ BIT(4)
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#define MAX3421E_SOFKAENAB BIT(3)
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#define MAX3421E_HUBPRE BIT(2)
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#define MAX3421E_LOWSPEED BIT(1)
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#define MAX3421E_HOST BIT(0)
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/* Register PERADDR */
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#define MAX3421E_REG_PERADDR 28U
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#define MAX3421E_PERADDR_MASK 0x7FU
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/* Register HCTL */
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#define MAX3421E_REG_HCTL 29U
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#define MAX3421E_SNDTOG1 BIT(7)
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#define MAX3421E_SNDTOG0 BIT(6)
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#define MAX3421E_RCVTOG1 BIT(5)
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#define MAX3421E_RCVTOG0 BIT(4)
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#define MAX3421E_SIGRSM BIT(3)
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#define MAX3421E_SAMPLEBUS BIT(2)
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#define MAX3421E_FRMRST BIT(1)
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#define MAX3421E_BUSRST BIT(0)
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/* Register HXFR */
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#define MAX3421E_REG_HXFR 30U
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#define MAX3421E_HS BIT(7)
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#define MAX3421E_ISO BIT(6)
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#define MAX3421E_OUTNIN BIT(5)
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#define MAX3421E_SETUP BIT(4)
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#define MAX3421E_EP_MASK 0x0FU
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#define MAX3421E_EP(ep) ((ep) & MAX3421E_EP_MASK)
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#define MAX3421E_HXFR_TYPE(hxfr) ((hxfr) & 0xF0U)
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#define MAX3421E_HXFR_SETUP(ep) (MAX3421E_SETUP | MAX3421E_EP(ep))
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#define MAX3421E_HXFR_BULKIN(ep) MAX3421E_EP(ep)
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#define MAX3421E_HXFR_ISOIN(ep) (MAX3421E_ISO | MAX3421E_EP(ep))
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#define MAX3421E_HXFR_HSIN(ep) (MAX3421E_HS | MAX3421E_EP(ep))
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#define MAX3421E_HXFR_BULKOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_BULKIN(ep))
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#define MAX3421E_HXFR_ISOOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_ISOIN(ep))
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#define MAX3421E_HXFR_HSOUT(ep) (MAX3421E_OUTNIN | MAX3421E_HXFR_HSIN(ep))
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#define MAX3421E_HXFR_TYPE_SETUP MAX3421E_SETUP
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#define MAX3421E_HXFR_TYPE_HSIN MAX3421E_HS
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#define MAX3421E_HXFR_TYPE_HSOUT (MAX3421E_OUTNIN | MAX3421E_HXFR_TYPE_HSIN)
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#define MAX3421E_HXFR_TYPE_ISOIN MAX3421E_ISO
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#define MAX3421E_HXFR_TYPE_ISOOUT (MAX3421E_OUTNIN | MAX3421E_HXFR_TYPE_ISOIN)
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#define MAX3421E_HXFR_TYPE_BULKIN 0
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#define MAX3421E_HXFR_TYPE_BULKOUT MAX3421E_OUTNIN
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/* Register HRSL */
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#define MAX3421E_REG_HRSL 31U
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#define MAX3421E_JKSTATUS_MASK (BIT(7) | BIT(6))
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#define MAX3421E_JSTATUS BIT(7)
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#define MAX3421E_KSTATUS BIT(6)
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#define MAX3421E_SNDTOGRD BIT(5)
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#define MAX3421E_RCVTOGRD BIT(4)
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#define MAX3421E_HRSLT_MASK 0x0FU
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#define MAX3421E_HRSLT(hr) ((hr) & MAX3421E_HRSLT_MASK)
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#define MAX3421E_HR_SUCCESS 0x00U
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#define MAX3421E_HR_BUSY 0x01U
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#define MAX3421E_HR_BADREQ 0x02U
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#define MAX3421E_HR_UNDEF 0x03U
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#define MAX3421E_HR_NAK 0x04U
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#define MAX3421E_HR_STALL 0x05U
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#define MAX3421E_HR_TOGERR 0x06U
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#define MAX3421E_HR_WRONGPID 0x07U
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#define MAX3421E_HR_BADBC 0x08U
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#define MAX3421E_HR_PIDERR 0x09U
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#define MAX3421E_HR_PKTERR 0x0AU
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#define MAX3421E_HR_CRCERR 0x0BU
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#define MAX3421E_HR_KERR 0x0CU
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#define MAX3421E_HR_JERR 0x0DU
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#define MAX3421E_HR_TIMEOUT 0x0EU
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#define MAX3421E_HR_BABBLE 0x0FU
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/* Successful Transfer */
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#define HRSLT_IS_SUCCESS(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_SUCCESS)
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/* SIE is busy, transfer pending */
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#define HRSLT_IS_BUSY(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BUSY)
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/* Bad value in HXFR reg */
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#define HRSLT_IS_BADREQ(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BADREQ)
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/* reserved */
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#define HRSLT_IS_UNDEF(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_UNDEF)
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/* Peripheral returned NAK */
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#define HRSLT_IS_NAK(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_NAK)
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/* Peripheral returned STALL */
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#define HRSLT_IS_STALL(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_STALL)
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/* Toggle error/ISO over-underrun */
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#define HRSLT_IS_TOGERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_TOGERR)
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/* Received the wrong PID */
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#define HRSLT_IS_WRONGPID(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_WRONGPID)
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/* Bad byte count */
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#define HRSLT_IS_BADBC(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BADBC)
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/* Receive PID is corrupted */
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#define HRSLT_IS_PIDERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_PIDERR)
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/* Packet error (stuff, EOP) */
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#define HRSLT_IS_PKTERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_PKTERR)
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/* CRC error */
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#define HRSLT_IS_CRCERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_CRCERR)
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/* K-state instead of response */
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#define HRSLT_IS_KERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_KERR)
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/* J-state instead of response */
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#define HRSLT_IS_JERR(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_JERR)
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/* Device did not respond in time */
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#define HRSLT_IS_TIMEOUT(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_TIMEOUT)
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/* Device talked too long */
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#define HRSLT_IS_BABBLE(hr) (MAX3421E_HRSLT(hr) == MAX3421E_HR_BABBLE)
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#endif /* ZEPHYR_INCLUDE_UHC_MAX3421E_H */
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