f817f62021
1. Due to the hardware limitations of the ATCSPI200 IP, the transmission and reception counts must be consistent. If there is a mismatch in length, dummy data needs to be transmitted or received. Under this limitation, using the spi_context_xx related APIs to determine whether the transmission is complete may cause issues in certain situations. Therefore, additional variables are set to record the exact number of bytes need to be transmitted or received. 2. Also, fix some inaccuracies in configuring DMA transfers. Signed-off-by: Kevin Wang <kevinwang821020@google.com>
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/*
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* Copyright (c) 2022 Andes Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_atcspi200);
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#include "spi_context.h"
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#include <zephyr/device.h>
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#include <zephyr/drivers/spi.h>
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#ifdef CONFIG_ANDES_SPI_DMA_MODE
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#include <zephyr/drivers/dma.h>
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#endif
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#define REG_TFMAT 0x10
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#define REG_TCTRL 0x20
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#define REG_CMD 0x24
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#define REG_DATA 0x2c
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#define REG_CTRL 0x30
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#define REG_STAT 0x34
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#define REG_INTEN 0x38
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#define REG_INTST 0x3c
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#define REG_TIMIN 0x40
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#define REG_CONFIG 0x7c
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#define SPI_TFMAT(base) (base + REG_TFMAT)
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#define SPI_TCTRL(base) (base + REG_TCTRL)
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#define SPI_CMD(base) (base + REG_CMD)
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#define SPI_DATA(base) (base + REG_DATA)
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#define SPI_CTRL(base) (base + REG_CTRL)
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#define SPI_STAT(base) (base + REG_STAT)
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#define SPI_INTEN(base) (base + REG_INTEN)
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#define SPI_INTST(base) (base + REG_INTST)
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#define SPI_TIMIN(base) (base + REG_TIMIN)
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#define SPI_CONFIG(base) (base + REG_CONFIG)
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/* Field mask of SPI transfer format register */
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#define TFMAT_DATA_LEN_OFFSET (8)
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#define TFMAT_CPHA_MSK BIT(0)
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#define TFMAT_CPOL_MSK BIT(1)
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#define TFMAT_SLVMODE_MSK BIT(2)
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#define TFMAT_LSB_MSK BIT(3)
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#define TFMAT_DATA_MERGE_MSK BIT(7)
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#define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
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#define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
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/* Field mask of SPI transfer control register */
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#define TCTRL_RD_TCNT_OFFSET (0)
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#define TCTRL_WR_TCNT_OFFSET (12)
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#define TCTRL_TRNS_MODE_OFFSET (24)
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#define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
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#define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
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/* Transfer mode */
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#define TRNS_MODE_WRITE_READ (0)
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#define TRNS_MODE_WRITE_ONLY (1)
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#define TRNS_MODE_READ_ONLY (2)
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/* Field mask of SPI interrupt enable register */
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#define IEN_RX_FIFO_MSK BIT(2)
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#define IEN_TX_FIFO_MSK BIT(3)
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#define IEN_END_MSK BIT(4)
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/* Field mask of SPI interrupt status register */
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#define INTST_RX_FIFO_INT_MSK BIT(2)
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#define INTST_TX_FIFO_INT_MSK BIT(3)
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#define INTST_END_INT_MSK BIT(4)
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/* Field mask of SPI config register */
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#define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
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#define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
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/* Field mask of SPI status register */
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#define STAT_RX_NUM_MSK GENMASK(12, 8)
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#define STAT_TX_NUM_MSK GENMASK(20, 16)
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/* Field mask of SPI control register */
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#define CTRL_RX_FIFO_RST_OFFSET (1)
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#define CTRL_TX_FIFO_RST_OFFSET (2)
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#define CTRL_RX_THRES_OFFSET (8)
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#define CTRL_TX_THRES_OFFSET (16)
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#define CTRL_RX_FIFO_RST_MSK BIT(1)
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#define CTRL_TX_FIFO_RST_MSK BIT(2)
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#define CTRL_RX_DMA_EN_MSK BIT(3)
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#define CTRL_TX_DMA_EN_MSK BIT(4)
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#define CTRL_RX_THRES_MSK GENMASK(12, 8)
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#define CTRL_TX_THRES_MSK GENMASK(20, 16)
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/* Field mask of SPI status register */
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#define TIMIN_SCLK_DIV_MSK GENMASK(7, 0)
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#define TX_FIFO_THRESHOLD (1)
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#define RX_FIFO_THRESHOLD (1)
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#define MAX_TRANSFER_CNT (512)
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#define MAX_CHAIN_SIZE (8)
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#define TX_FIFO_SIZE_SETTING(base) \
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(sys_read32(SPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK)
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#define TX_FIFO_SIZE(base) \
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(2 << (TX_FIFO_SIZE_SETTING(base) >> 4))
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#define RX_FIFO_SIZE_SETTING(base) \
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(sys_read32(SPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK)
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#define RX_FIFO_SIZE(base) \
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(2 << (RX_FIFO_SIZE_SETTING(base) >> 0))
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#define TX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_TX_NUM_MSK)
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#define RX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_RX_NUM_MSK)
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#define GET_TX_NUM(base) (TX_NUM_STAT(base) >> 16)
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#define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8)
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