a897005b98
The receiver ready flag of the (channel) status register for the sam controller was not being interpreted correctly for both the uart and usart implementation, according to the uart api. Tested and confirmed using the sam4sa16ca. Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
496 lines
12 KiB
C
496 lines
12 KiB
C
/*
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* Copyright (c) 2017 Piotr Mienkowski
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* Copyright (c) 2018 Justin Watson
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* Copyright (c) 2023 Gerson Fernando Budke
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_uart
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/** @file
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* @brief UART driver for Atmel SAM MCU family.
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*/
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#include <errno.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
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#include <zephyr/irq.h>
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/* Device constant configuration parameters */
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struct uart_sam_dev_cfg {
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Uart *regs;
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const struct atmel_sam_pmc_config clock_cfg;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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};
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/* Device run time data */
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struct uart_sam_dev_data {
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uint32_t baud_rate;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_cb; /* Interrupt Callback */
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void *irq_cb_data; /* Interrupt Callback Arg */
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int uart_sam_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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Uart * const uart = cfg->regs;
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if (!(uart->UART_SR & UART_SR_RXRDY)) {
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return -1;
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}
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/* got a character */
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*c = (unsigned char)uart->UART_RHR;
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return 0;
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}
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static void uart_sam_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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Uart * const uart = cfg->regs;
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/* Wait for transmitter to be ready */
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while (!(uart->UART_SR & UART_SR_TXRDY)) {
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}
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/* send a character */
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uart->UART_THR = (uint32_t)c;
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}
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static int uart_sam_err_check(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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int errors = 0;
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if (uart->UART_SR & UART_SR_OVRE) {
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errors |= UART_ERROR_OVERRUN;
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}
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if (uart->UART_SR & UART_SR_PARE) {
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errors |= UART_ERROR_PARITY;
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}
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if (uart->UART_SR & UART_SR_FRAME) {
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errors |= UART_ERROR_FRAMING;
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}
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uart->UART_CR = UART_CR_RSTSTA;
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return errors;
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}
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static int uart_sam_baudrate_set(const struct device *dev, uint32_t baudrate)
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{
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struct uart_sam_dev_data *const dev_data = dev->data;
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uint32_t divisor;
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__ASSERT(baudrate,
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"baud rate has to be bigger than 0");
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__ASSERT(SOC_ATMEL_SAM_MCK_FREQ_HZ/16U >= baudrate,
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"MCK frequency is too small to set required baud rate");
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divisor = SOC_ATMEL_SAM_MCK_FREQ_HZ / 16U / baudrate;
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if (divisor > 0xFFFF) {
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return -EINVAL;
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}
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uart->UART_BRGR = UART_BRGR_CD(divisor);
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dev_data->baud_rate = baudrate;
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return 0;
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}
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static uint32_t uart_sam_cfg2sam_parity(uint8_t parity)
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{
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switch (parity) {
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case UART_CFG_PARITY_EVEN:
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return UART_MR_PAR_EVEN;
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case UART_CFG_PARITY_ODD:
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return UART_MR_PAR_ODD;
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case UART_CFG_PARITY_SPACE:
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return UART_MR_PAR_SPACE;
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case UART_CFG_PARITY_MARK:
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return UART_MR_PAR_MARK;
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case UART_CFG_PARITY_NONE:
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default:
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return UART_MR_PAR_NO;
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}
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}
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static uint8_t uart_sam_get_parity(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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switch (uart->UART_MR & UART_MR_PAR_Msk) {
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case UART_MR_PAR_EVEN:
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return UART_CFG_PARITY_EVEN;
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case UART_MR_PAR_ODD:
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return UART_CFG_PARITY_ODD;
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case UART_MR_PAR_SPACE:
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return UART_CFG_PARITY_SPACE;
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case UART_MR_PAR_MARK:
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return UART_CFG_PARITY_MARK;
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case UART_MR_PAR_NO:
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default:
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return UART_CFG_PARITY_NONE;
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}
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}
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static int uart_sam_configure(const struct device *dev,
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const struct uart_config *cfg)
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{
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int retval;
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const struct uart_sam_dev_cfg *const config = dev->config;
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volatile Uart * const uart = config->regs;
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/* Driver only supports 8 data bits, 1 stop bit, and no flow control */
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if (cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
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cfg->data_bits != UART_CFG_DATA_BITS_8 ||
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cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOTSUP;
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}
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/* Reset and disable UART */
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uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX
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| UART_CR_RXDIS | UART_CR_TXDIS
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| UART_CR_RSTSTA;
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/* baud rate driven by the peripheral clock, UART does not filter
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* the receive line, parity chosen by config
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*/
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uart->UART_MR = UART_MR_CHMODE_NORMAL
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| uart_sam_cfg2sam_parity(cfg->parity);
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/* Set baud rate */
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retval = uart_sam_baudrate_set(dev, cfg->baudrate);
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if (retval != 0) {
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return retval;
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}
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/* Enable receiver and transmitter */
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uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
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return 0;
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}
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static int uart_sam_config_get(const struct device *dev,
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struct uart_config *cfg)
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{
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struct uart_sam_dev_data *const dev_data = dev->data;
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cfg->baudrate = dev_data->baud_rate;
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cfg->parity = uart_sam_get_parity(dev);
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/* only supported mode for this peripheral */
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cfg->stop_bits = UART_CFG_STOP_BITS_1;
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cfg->data_bits = UART_CFG_DATA_BITS_8;
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
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return 0;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_sam_fifo_fill(const struct device *dev,
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const uint8_t *tx_data,
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int size)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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/* Wait for transmitter to be ready. */
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while ((uart->UART_SR & UART_SR_TXRDY) == 0) {
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}
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uart->UART_THR = *tx_data;
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return 1;
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}
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static int uart_sam_fifo_read(const struct device *dev, uint8_t *rx_data,
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const int size)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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int bytes_read;
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bytes_read = 0;
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while (bytes_read < size) {
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if (uart->UART_SR & UART_SR_RXRDY) {
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rx_data[bytes_read] = uart->UART_RHR;
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bytes_read++;
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} else {
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break;
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}
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}
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return bytes_read;
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}
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static void uart_sam_irq_tx_enable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IER = UART_IER_TXRDY;
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}
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static void uart_sam_irq_tx_disable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IDR = UART_IDR_TXRDY;
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}
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static int uart_sam_irq_tx_ready(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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/* Check that the transmitter is ready but only
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* return true if the interrupt is also enabled
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*/
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return (uart->UART_SR & UART_SR_TXRDY &&
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uart->UART_IMR & UART_IMR_TXRDY);
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}
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static void uart_sam_irq_rx_enable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IER = UART_IER_RXRDY;
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}
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static void uart_sam_irq_rx_disable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IDR = UART_IDR_RXRDY;
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}
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static int uart_sam_irq_tx_complete(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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return (uart->UART_SR & UART_SR_TXRDY &&
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uart->UART_IMR & UART_IMR_TXEMPTY);
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}
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static int uart_sam_irq_rx_ready(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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return (uart->UART_SR & UART_SR_RXRDY);
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}
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static void uart_sam_irq_err_enable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IER = UART_IER_OVRE | UART_IER_FRAME | UART_IER_PARE;
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}
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static void uart_sam_irq_err_disable(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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uart->UART_IDR = UART_IDR_OVRE | UART_IDR_FRAME | UART_IDR_PARE;
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}
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static int uart_sam_irq_is_pending(const struct device *dev)
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{
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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volatile Uart * const uart = cfg->regs;
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return (uart->UART_IMR & (UART_IMR_TXRDY | UART_IMR_RXRDY)) &
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(uart->UART_SR & (UART_SR_TXRDY | UART_SR_RXRDY));
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}
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static int uart_sam_irq_update(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static void uart_sam_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_sam_dev_data *const dev_data = dev->data;
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dev_data->irq_cb = cb;
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dev_data->irq_cb_data = cb_data;
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}
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static void uart_sam_isr(const struct device *dev)
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{
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struct uart_sam_dev_data *const dev_data = dev->data;
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if (dev_data->irq_cb) {
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dev_data->irq_cb(dev, dev_data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static int uart_sam_init(const struct device *dev)
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{
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int retval;
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const struct uart_sam_dev_cfg *const cfg = dev->config;
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struct uart_sam_dev_data *const dev_data = dev->data;
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Uart * const uart = cfg->regs;
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/* Enable UART clock in PMC */
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(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
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(clock_control_subsys_t)&cfg->clock_cfg);
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/* Connect pins to the peripheral */
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retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (retval < 0) {
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return retval;
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}
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/* Disable Interrupts */
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uart->UART_IDR = 0xFFFFFFFF;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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cfg->irq_config_func(dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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struct uart_config uart_config = {
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.baudrate = dev_data->baud_rate,
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.parity = UART_CFG_PARITY_NONE,
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.stop_bits = UART_CFG_STOP_BITS_1,
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.data_bits = UART_CFG_DATA_BITS_8,
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.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,
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};
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return uart_sam_configure(dev, &uart_config);
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}
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static const struct uart_driver_api uart_sam_driver_api = {
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.poll_in = uart_sam_poll_in,
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.poll_out = uart_sam_poll_out,
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.err_check = uart_sam_err_check,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = uart_sam_configure,
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.config_get = uart_sam_config_get,
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_sam_fifo_fill,
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.fifo_read = uart_sam_fifo_read,
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.irq_tx_enable = uart_sam_irq_tx_enable,
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.irq_tx_disable = uart_sam_irq_tx_disable,
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.irq_tx_ready = uart_sam_irq_tx_ready,
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.irq_rx_enable = uart_sam_irq_rx_enable,
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.irq_rx_disable = uart_sam_irq_rx_disable,
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.irq_tx_complete = uart_sam_irq_tx_complete,
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.irq_rx_ready = uart_sam_irq_rx_ready,
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.irq_err_enable = uart_sam_irq_err_enable,
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.irq_err_disable = uart_sam_irq_err_disable,
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.irq_is_pending = uart_sam_irq_is_pending,
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.irq_update = uart_sam_irq_update,
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.irq_callback_set = uart_sam_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define UART_SAM_DECLARE_CFG(n, IRQ_FUNC_INIT) \
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static const struct uart_sam_dev_cfg uart##n##_sam_config = { \
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.regs = (Uart *)DT_INST_REG_ADDR(n), \
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.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n), \
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\
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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\
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IRQ_FUNC_INIT \
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define UART_SAM_CONFIG_FUNC(n) \
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static void uart##n##_sam_irq_config_func(const struct device *port) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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uart_sam_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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}
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#define UART_SAM_IRQ_CFG_FUNC_INIT(n) \
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.irq_config_func = uart##n##_sam_irq_config_func
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#define UART_SAM_INIT_CFG(n) \
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UART_SAM_DECLARE_CFG(n, UART_SAM_IRQ_CFG_FUNC_INIT(n))
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#else
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#define UART_SAM_CONFIG_FUNC(n)
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#define UART_SAM_IRQ_CFG_FUNC_INIT
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#define UART_SAM_INIT_CFG(n) \
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UART_SAM_DECLARE_CFG(n, UART_SAM_IRQ_CFG_FUNC_INIT)
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#endif
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#define UART_SAM_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static struct uart_sam_dev_data uart##n##_sam_data = { \
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.baud_rate = DT_INST_PROP(n, current_speed), \
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}; \
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\
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static const struct uart_sam_dev_cfg uart##n##_sam_config; \
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\
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DEVICE_DT_INST_DEFINE(n, &uart_sam_init, \
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NULL, &uart##n##_sam_data, \
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&uart##n##_sam_config, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_sam_driver_api); \
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\
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UART_SAM_CONFIG_FUNC(n) \
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\
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UART_SAM_INIT_CFG(n);
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DT_INST_FOREACH_STATUS_OKAY(UART_SAM_INIT)
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