dc4e092830
Initial SAU UART driver support for Renesas RA0 series Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com> Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
591 lines
22 KiB
C
591 lines
22 KiB
C
/*
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* Copyright (c) 2026 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_uart_sau
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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#include <r_sau_uart.h>
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LOG_MODULE_REGISTER(renesas_ra_uart_sau, CONFIG_UART_LOG_LEVEL);
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#define SAU_UART_STCLK_MAX (127)
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#define SAU_UART_STCLK_MIN (2)
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typedef R_SAU0_Type uart_renesas_ra_sau_regs_t;
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struct uart_renesas_ra_sau_config {
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const struct device *clock_dev;
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const struct clock_control_ra_subsys_cfg clock_subsys;
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const struct pinctrl_dev_config *pincfg;
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uart_renesas_ra_sau_regs_t *const regs;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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void (*irq_config_func)(const struct device *dev);
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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uint8_t tx_channel;
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uint8_t rx_channel;
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};
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struct uart_renesas_ra_sau_data {
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struct uart_config uart_cfg;
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sau_uart_instance_ctrl_t fsp_ctrl;
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uart_cfg_t fsp_cfg;
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sau_uart_extended_cfg_t fsp_extend_cfg;
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sau_uart_baudrate_setting_t fsp_baud_setting;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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uart_irq_callback_user_data_t user_cb;
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void *user_cb_data;
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int uart_renesas_ra_sau_baudrate_validate(const struct device *dev, uint32_t baudrate,
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sau_uart_baudrate_setting_t *const p_baud_setting)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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uint32_t peripheral_clock;
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uint8_t stclk;
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int ret;
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ret = clock_control_get_rate(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys,
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&peripheral_clock);
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if (ret < 0) {
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LOG_ERR("Failed to get peripheral clock rate: %d", ret);
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return ret;
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}
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stclk = DIV_ROUND_CLOSEST(peripheral_clock, (2 * baudrate)) - 1;
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if (stclk < SAU_UART_STCLK_MIN || stclk > SAU_UART_STCLK_MAX) {
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LOG_ERR("SAU UART baudrate of %u is not achievable with selected operation clock "
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"settings. Suggest stclk >= %hu and stclk <= %hu. Calculated stclk: %u",
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baudrate, SAU_UART_STCLK_MIN, SAU_UART_STCLK_MAX, stclk);
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return -EINVAL;
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}
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p_baud_setting->stclk = stclk;
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return 0;
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}
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static int uart_renesas_ra_sau_apply_config(const struct device *dev,
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const struct uart_config *uart_cfg)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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uart_data_bits_t data_bits;
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uart_parity_t parity;
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fsp_err_t fsp_err;
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int ret;
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if (uart_cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
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return -ENOSYS;
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}
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if (uart_cfg->stop_bits != UART_CFG_STOP_BITS_1) {
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return -ENOSYS;
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}
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/* If already open, check if the configuration is the same to prevent reconfiguration */
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if (data->fsp_ctrl.open != 0) {
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if (memcmp(&data->uart_cfg, uart_cfg, sizeof(struct uart_config)) == 0) {
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return 0;
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}
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}
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switch (uart_cfg->data_bits) {
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case UART_CFG_DATA_BITS_7:
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data_bits = UART_DATA_BITS_7;
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break;
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case UART_CFG_DATA_BITS_8:
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data_bits = UART_DATA_BITS_8;
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break;
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default:
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LOG_ERR("Unsupported data bits setting");
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return -ENOSYS;
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}
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switch (uart_cfg->parity) {
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case UART_CFG_PARITY_NONE:
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parity = UART_PARITY_OFF;
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break;
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case UART_CFG_PARITY_EVEN:
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parity = UART_PARITY_EVEN;
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break;
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case UART_CFG_PARITY_ODD:
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parity = UART_PARITY_ODD;
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break;
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default:
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LOG_ERR("Unsupported parity setting");
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return -ENOSYS;
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}
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ret = uart_renesas_ra_sau_baudrate_validate(dev, uart_cfg->baudrate,
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&data->fsp_baud_setting);
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if (ret < 0) {
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LOG_ERR("Failed to calculate baudrate settings");
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return ret;
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}
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/* If the UART is already open, close it before applying new configuration */
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if (data->fsp_ctrl.open != 0) {
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fsp_err = R_SAU_UART_Close(&data->fsp_ctrl);
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if (fsp_err != FSP_SUCCESS) {
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return -EIO;
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}
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}
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/* Update the new configuration to the data structure */
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data->fsp_cfg.data_bits = data_bits;
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data->fsp_cfg.parity = parity;
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/* Open the UART with the new configuration */
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fsp_err = R_SAU_UART_Open(&data->fsp_ctrl, &data->fsp_cfg);
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if (fsp_err != FSP_SUCCESS) {
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return -EIO;
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}
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memcpy(&data->uart_cfg, uart_cfg, sizeof(struct uart_config));
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return 0;
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}
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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void uart_renesas_ra_sau_isr(struct device *dev)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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if (data->user_cb != NULL) {
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data->user_cb(dev, data->user_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static int uart_renesas_ra_sau_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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int ret = -1;
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/* Check if the receive data register is full */
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if (cfg->regs->SSR_b[cfg->rx_channel].BFF == 1) {
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*c = (unsigned char)cfg->regs->SDR_b[cfg->rx_channel].DAT;
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ret = 0;
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}
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return ret;
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}
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static void uart_renesas_ra_sau_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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uart_renesas_ra_sau_regs_t *const regs = cfg->regs;
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/* Wait until the transmit buffer is empty */
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while (regs->SSR_b[cfg->tx_channel].BFF != 0) {
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}
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regs->SDR_b[cfg->tx_channel].DAT = c;
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}
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static int uart_renesas_ra_sau_err_check(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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const uint16_t ssr_reg = cfg->regs->SSR[cfg->rx_channel];
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int err = 0;
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uint8_t flag_clear = 0U;
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if (ssr_reg == 0) {
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return 0;
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}
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if (R_SAU0_SSR_OVF_Msk & ssr_reg) {
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flag_clear |= R_SAU0_SSR_OVF_Msk;
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err |= UART_ERROR_OVERRUN;
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}
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if (R_SAU0_SSR_PEF_Msk & ssr_reg) {
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flag_clear |= R_SAU0_SSR_PEF_Msk;
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err |= UART_ERROR_PARITY;
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}
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if (R_SAU0_SSR_FEF_Msk & ssr_reg) {
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flag_clear |= R_SAU0_SSR_FEF_Msk;
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err |= UART_ERROR_FRAMING;
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}
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/* The data buffer must be read as part of clearing
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* the error to avoid an overrun error after recovery.
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*/
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cfg->regs->SDR_b[cfg->rx_channel].DAT;
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/* Clear the error flags */
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cfg->regs->SIR[cfg->rx_channel] = flag_clear;
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return err;
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}
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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static int uart_renesas_ra_sau_configure(const struct device *dev, const struct uart_config *cfg)
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{
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return uart_renesas_ra_sau_apply_config(dev, cfg);
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}
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static int uart_renesas_ra_sau_config_get(const struct device *dev, struct uart_config *cfg)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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*cfg = data->uart_cfg;
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return 0;
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_renesas_ra_sau_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb, void *cb_data)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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unsigned int key;
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key = irq_lock();
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data->user_cb = cb;
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data->user_cb_data = cb_data;
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irq_unlock(key);
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}
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static void uart_renesas_ra_sau_irq_tx_enable(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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struct uart_renesas_ra_sau_data *data = dev->data;
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cfg->regs->SMR[cfg->tx_channel] |= R_SAU0_SMR_MD0_Msk;
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/* Enable TX interrupt */
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irq_enable((uint32_t)data->fsp_cfg.txi_irq);
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}
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static void uart_renesas_ra_sau_irq_tx_disable(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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struct uart_renesas_ra_sau_data *data = dev->data;
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cfg->regs->SMR[cfg->tx_channel] &= ~R_SAU0_SMR_MD0_Msk;
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/* Disable TX interrupt */
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irq_disable((uint32_t)data->fsp_cfg.txi_irq);
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}
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static void uart_renesas_ra_sau_irq_rx_enable(const struct device *dev)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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/* Enable RX interrupt */
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irq_enable((uint32_t)data->fsp_cfg.rxi_irq);
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}
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static void uart_renesas_ra_sau_irq_rx_disable(const struct device *dev)
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{
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struct uart_renesas_ra_sau_data *data = dev->data;
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/* Disable RX interrupt */
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irq_disable((uint32_t)data->fsp_cfg.rxi_irq);
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}
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static void uart_renesas_ra_sau_irq_err_enable(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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/* Enable error interrupt */
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cfg->regs->SCR[cfg->rx_channel] |= R_SAU0_SCR_EOC_Msk;
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}
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static void uart_renesas_ra_sau_irq_err_disable(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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/* Disable error interrupt */
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cfg->regs->SCR[cfg->rx_channel] &= ~R_SAU0_SCR_EOC_Msk;
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}
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static int uart_renesas_ra_sau_irq_update(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 1;
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}
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static int uart_renesas_ra_sau_irq_is_pending(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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struct uart_renesas_ra_sau_data *data = dev->data;
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const uint16_t tx_ssr = cfg->regs->SSR[cfg->tx_channel];
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const uint16_t rx_ssr = cfg->regs->SSR[cfg->rx_channel];
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const uint16_t rx_scr = cfg->regs->SCR[cfg->rx_channel];
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/* Check TX buffer full interrupt flag - pending when BFF = 0 (empty) */
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bool tx_pending =
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!(tx_ssr & R_SAU0_SSR_BFF_Msk) && irq_is_enabled((uint32_t)data->fsp_cfg.txi_irq);
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/* Check RX buffer full interrupt flag - pending when BFF = 1 (full) */
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bool rx_pending = !!(rx_ssr & (R_SAU0_SSR_BFF_Msk)) &&
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irq_is_enabled((uint32_t)data->fsp_cfg.rxi_irq);
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/* Check error interrupt flags - pending when one or more error flags are set */
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bool err_pending =
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!!(rx_ssr & (R_SAU0_SSR_OVF_Msk | R_SAU0_SSR_PEF_Msk | R_SAU0_SSR_FEF_Msk)) &&
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!!(rx_scr & R_SAU0_SCR_EOC_Msk);
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return (tx_pending || rx_pending || err_pending);
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}
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static int uart_renesas_ra_sau_irq_tx_ready(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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uart_renesas_ra_sau_regs_t *const regs = cfg->regs;
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/* Check whether the transmit buffer is empty */
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if (regs->SSR_b[cfg->tx_channel].BFF == 0) {
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return 1;
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}
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return 0;
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}
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static int uart_renesas_ra_sau_irq_rx_ready(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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/* Check whether the receive buffer is full */
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return (cfg->regs->SSR_b[cfg->rx_channel].BFF == 1);
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}
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static int uart_renesas_ra_sau_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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int ret = 0;
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/* Check whether the transmit buffer is empty and fill it */
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if ((size > 0) && (cfg->regs->SSR_b[cfg->tx_channel].BFF == 0)) {
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cfg->regs->SDR_b[cfg->tx_channel].DAT = *tx_data;
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ret = 1;
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}
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return ret;
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}
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static int uart_renesas_ra_sau_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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int ret = 0;
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/* Check whether the receive buffer is full and read from it */
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if ((size > 0) && (cfg->regs->SSR_b[cfg->rx_channel].BFF == 1)) {
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*rx_data = cfg->regs->SDR_b[cfg->rx_channel].DAT;
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ret = 1;
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}
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return ret;
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}
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static int uart_renesas_ra_sau_irq_tx_complete(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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/* Check whether transmit is complete */
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return (cfg->regs->SSR_b[cfg->tx_channel].TSF == 0);
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static DEVICE_API(uart, uart_renesas_ra_sau_driver_api) = {
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.poll_in = uart_renesas_ra_sau_poll_in,
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.poll_out = uart_renesas_ra_sau_poll_out,
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.err_check = uart_renesas_ra_sau_err_check,
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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.configure = uart_renesas_ra_sau_configure,
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.config_get = uart_renesas_ra_sau_config_get,
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_renesas_ra_sau_fifo_fill,
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.fifo_read = uart_renesas_ra_sau_fifo_read,
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.irq_tx_enable = uart_renesas_ra_sau_irq_tx_enable,
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.irq_tx_disable = uart_renesas_ra_sau_irq_tx_disable,
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.irq_tx_ready = uart_renesas_ra_sau_irq_tx_ready,
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.irq_rx_enable = uart_renesas_ra_sau_irq_rx_enable,
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.irq_rx_disable = uart_renesas_ra_sau_irq_rx_disable,
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.irq_tx_complete = uart_renesas_ra_sau_irq_tx_complete,
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.irq_rx_ready = uart_renesas_ra_sau_irq_rx_ready,
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.irq_err_enable = uart_renesas_ra_sau_irq_err_enable,
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.irq_err_disable = uart_renesas_ra_sau_irq_err_disable,
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.irq_is_pending = uart_renesas_ra_sau_irq_is_pending,
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.irq_update = uart_renesas_ra_sau_irq_update,
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.irq_callback_set = uart_renesas_ra_sau_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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static int uart_renesas_ra_sau_init(const struct device *dev)
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{
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const struct uart_renesas_ra_sau_config *cfg = dev->config;
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struct uart_renesas_ra_sau_data *data = dev->data;
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int ret;
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ret = clock_control_on(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys);
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if (ret < 0) {
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return ret;
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}
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ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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ret = uart_renesas_ra_sau_apply_config(dev, &data->uart_cfg);
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if (ret < 0) {
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return ret;
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}
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
|
|
cfg->irq_config_func(dev);
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define UART_RENESAS_RA_SAU_TX_IRQ_GET(idx, cell) \
|
|
DT_IRQ(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0), cell)
|
|
|
|
#define UART_RENESAS_RA_SAU_RX_IRQ_GET(idx, cell) \
|
|
DT_IRQ(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 1), cell)
|
|
|
|
#define UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx) \
|
|
DT_CLOCKS_CTLR(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0))
|
|
|
|
#define UART_RENESAS_RA_SAU_RX_CLOCK_CTRL(idx) \
|
|
DT_CLOCKS_CTLR(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 1))
|
|
|
|
#define RENESAS_RA_SAU_UART_BIR_ORDER_GET(idx) \
|
|
COND_CODE_1(DT_INST_PROP(idx, msb_first), (SAU_UART_DATA_SEQUENCE_MSB), \
|
|
(SAU_UART_DATA_SEQUENCE_LSB))
|
|
|
|
#define RENESAS_RA_SAU_UART_TX_SIGNAL_LEVEL_GET(idx) \
|
|
COND_CODE_1(DT_INST_PROP(idx, tx_signal_inversion), (SAU_UART_SIGNAL_LEVEL_INVERTED), \
|
|
(SAU_UART_SIGNAL_LEVEL_STANDARD))
|
|
|
|
#define RENESAS_RA_SAU_UART_CHECK_OPERATION_CLOCK(idx) \
|
|
BUILD_ASSERT( \
|
|
(IS_EQ(DT_PROP(DT_PARENT(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0)), unit), 0) \
|
|
? (DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), \
|
|
DT_NODELABEL(sau_ck00)) || \
|
|
DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), \
|
|
DT_NODELABEL(sau_ck01))) \
|
|
: (IS_EQ(DT_PROP(DT_PARENT(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0)), \
|
|
unit), \
|
|
1) \
|
|
? (DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), \
|
|
DT_NODELABEL(sau_ck10)) || \
|
|
DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), \
|
|
DT_NODELABEL(sau_ck11))) \
|
|
: 0)), \
|
|
"operation_clock not supported")
|
|
|
|
#define RENESAS_RA_SAU_UART_OPERATION_CLOCK(idx) \
|
|
(DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), DT_NODELABEL(sau_ck00)) || \
|
|
DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), DT_NODELABEL(sau_ck10))) \
|
|
? SAU_UART_OPERATION_CLOCK_CK0 \
|
|
: SAU_UART_OPERATION_CLOCK_CK1
|
|
|
|
#if !defined(CONFIG_UART_INTERRUPT_DRIVEN)
|
|
#define UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_DEFINE(idx)
|
|
#define UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_GET(idx)
|
|
#else
|
|
#define UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_DEFINE(idx) \
|
|
static void uart_renesas_ra_sau_irq_configure_##idx(const struct device *dev) \
|
|
{ \
|
|
IRQ_CONNECT(UART_RENESAS_RA_SAU_RX_IRQ_GET(idx, irq), \
|
|
UART_RENESAS_RA_SAU_RX_IRQ_GET(idx, priority), \
|
|
uart_renesas_ra_sau_isr, DEVICE_DT_INST_GET(idx), 0); \
|
|
\
|
|
IRQ_CONNECT(UART_RENESAS_RA_SAU_TX_IRQ_GET(idx, irq), \
|
|
UART_RENESAS_RA_SAU_TX_IRQ_GET(idx, priority), \
|
|
uart_renesas_ra_sau_isr, DEVICE_DT_INST_GET(idx), 0); \
|
|
\
|
|
IRQ_CONNECT(DT_INST_IRQ(idx, irq), DT_INST_IRQ(idx, priority), \
|
|
uart_renesas_ra_sau_isr, DEVICE_DT_INST_GET(idx), 0); \
|
|
irq_enable(DT_INST_IRQ(idx, irq)); \
|
|
}
|
|
|
|
#define UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_GET(idx) \
|
|
.irq_config_func = uart_renesas_ra_sau_irq_configure_##idx
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
#define UART_RENESAS_RA_SAU_INIT(idx) \
|
|
BUILD_ASSERT( \
|
|
DT_SAME_NODE(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx), \
|
|
UART_RENESAS_RA_SAU_RX_CLOCK_CTRL(idx)), \
|
|
"SAU UART TX and SAU UART RX must have the same clock sources on device tree"); \
|
|
\
|
|
RENESAS_RA_SAU_UART_CHECK_OPERATION_CLOCK(idx); \
|
|
\
|
|
UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_DEFINE(idx) \
|
|
PINCTRL_DT_DEFINE(DT_DRV_INST(idx)); \
|
|
static const struct uart_renesas_ra_sau_config uart_renesas_ra_sau_config_##idx = { \
|
|
.pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(idx)), \
|
|
.clock_dev = DEVICE_DT_GET(UART_RENESAS_RA_SAU_TX_CLOCK_CTRL(idx)), \
|
|
.clock_subsys = \
|
|
{ \
|
|
.mstp = (uint32_t)DT_CLOCKS_CELL_BY_IDX( \
|
|
DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0), 0, mstp), \
|
|
.stop_bit = DT_CLOCKS_CELL_BY_IDX( \
|
|
DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0), 0, \
|
|
stop_bit), \
|
|
}, \
|
|
.regs = (uart_renesas_ra_sau_regs_t *)DT_REG_ADDR( \
|
|
DT_PARENT(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0))), \
|
|
.tx_channel = DT_REG_ADDR(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 0)), \
|
|
.rx_channel = DT_REG_ADDR(DT_INST_PHANDLE_BY_IDX(idx, sau_channels, 1)), \
|
|
UART_RENESAS_RA_SAU_IRQ_CONFIG_FUNC_GET(idx)}; \
|
|
\
|
|
static struct uart_renesas_ra_sau_data uart_renesas_ra_sau_data_##idx = { \
|
|
.uart_cfg = \
|
|
{ \
|
|
.baudrate = DT_INST_PROP(idx, current_speed), \
|
|
.parity = DT_INST_ENUM_IDX(idx, parity), \
|
|
.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits), \
|
|
.data_bits = DT_INST_ENUM_IDX(idx, data_bits), \
|
|
.flow_ctrl = DT_INST_PROP(idx, hw_flow_control) \
|
|
? UART_CFG_FLOW_CTRL_RTS_CTS \
|
|
: UART_CFG_FLOW_CTRL_NONE, \
|
|
}, \
|
|
.fsp_baud_setting = \
|
|
{ \
|
|
.operation_clock = RENESAS_RA_SAU_UART_OPERATION_CLOCK(idx), \
|
|
}, \
|
|
.fsp_extend_cfg = \
|
|
{ \
|
|
.sequence = RENESAS_RA_SAU_UART_BIR_ORDER_GET(idx), \
|
|
.signal_level = RENESAS_RA_SAU_UART_TX_SIGNAL_LEVEL_GET(idx), \
|
|
.p_baudrate = &uart_renesas_ra_sau_data_##idx.fsp_baud_setting, \
|
|
}, \
|
|
.fsp_cfg = \
|
|
{ \
|
|
.channel = DT_INST_REG_ADDR(idx), \
|
|
.rxi_ipl = UART_RENESAS_RA_SAU_RX_IRQ_GET(idx, priority), \
|
|
.rxi_irq = UART_RENESAS_RA_SAU_RX_IRQ_GET(idx, irq), \
|
|
.txi_ipl = UART_RENESAS_RA_SAU_TX_IRQ_GET(idx, priority), \
|
|
.txi_irq = UART_RENESAS_RA_SAU_TX_IRQ_GET(idx, irq), \
|
|
.eri_ipl = BSP_IRQ_DISABLED, \
|
|
.eri_irq = FSP_INVALID_VECTOR, \
|
|
.p_extend = &uart_renesas_ra_sau_data_##idx.fsp_extend_cfg, \
|
|
.p_context = NULL, \
|
|
.p_transfer_tx = NULL, \
|
|
.p_transfer_rx = NULL, \
|
|
}, \
|
|
}; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(idx, uart_renesas_ra_sau_init, NULL, \
|
|
&uart_renesas_ra_sau_data_##idx, &uart_renesas_ra_sau_config_##idx, \
|
|
PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
|
|
&uart_renesas_ra_sau_driver_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(UART_RENESAS_RA_SAU_INIT)
|