bda3b101d3
At present, many of the NXP S32 shim drivers do not make use of devicetree instance-based macros because the NXP S32 HAL relies on an index-based approach, requiring knowledge of the peripheral instance index during both compilation and runtime, and this index might not align with the devicetree instance index. The proposed solution in this patch eliminates this limitation by determining the peripheral instance index during compilation through macrobatics and defining the driver's ISR within the shim driver itself. Note that for some peripheral instances is needed to redefine the HAL macros of the peripheral base address, since the naming is not uniform for all instances. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
39 lines
890 B
C
39 lines
890 B
C
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_
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struct uart_nxp_s32_config {
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uint32_t instance;
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LINFLEXD_Type *base;
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const struct pinctrl_dev_config *pincfg;
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Linflexd_Uart_Ip_UserConfigType hw_cfg;
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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struct uart_nxp_s32_int {
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bool tx_fifo_busy;
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bool rx_fifo_busy;
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bool irq_tx_enable;
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bool irq_rx_enable;
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uint8_t rx_fifo_data;
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};
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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struct uart_nxp_s32_data {
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struct uart_nxp_s32_int int_data;
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uart_irq_callback_user_data_t callback;
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void *cb_data;
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};
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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extern Linflexd_Uart_Ip_StateStructureType
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Linflexd_Uart_Ip_apStateStructure[LINFLEXD_UART_IP_NUMBER_OF_INSTANCES];
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_ */
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