d6f8e9ae5b
This driver exposes STM32 RCC reset functionality through reset API. Information about RCC register offset and bit is encoded just like GD32. The first 5 least significant bits contains register bit number. Next 12 bits are used to keep RCC register offset. Remaining bits are unused. Signed-off-by: Patryk Duda <pdk@semihalf.com>
8 lines
184 B
Plaintext
8 lines
184 B
Plaintext
# Copyright (c) 2022 Google Inc
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# SPDX-License-Identifier: Apache-2.0
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config RESET_STM32
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bool "STM32 Reset Controller Driver"
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default y
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depends on DT_HAS_ST_STM32_RCC_RCTL_ENABLED
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